This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

[PATCH][ARM][5/n] Partial IT block deprecation in ARMv8 AArch32 - load/store multiple

From: "Kyrylo Tkachov" <kyrylo dot tkachov at arm dot com>
To: <gcc-patches at gcc dot gnu dot org>
Cc: "Richard Earnshaw" <Richard dot Earnshaw at arm dot com>, "Ramana Radhakrishnan" <Ramana dot Radhakrishnan at arm dot com>
Date: Thu, 6 Jun 2013 14:36:52 +0100
Subject: [PATCH][ARM][5/n] Partial IT block deprecation in ARMv8 AArch32 - load/store multiple

Hi all,

This patch updates the fixed-point math patterns in arm-fixed.md to
conform to new IT block rules in ARMv8. The add/sub instructions can be
placed in an IT block if they use the low registers.
The other more exotic variants (ssub, uqadd etc) do not have 16-bit
encodings and can therefore not be conditionalised by the new rules.

Tested together with the other patches in the series by bootstrap on a
Cortex-A15 and regtest arm-none-eabi on qemu and model.

Ok for trunk?


Thanks,
Kyrill


2013-06-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3,
	sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift,
arm_usatsihi):
	Adjust alternatives for arm_restrict_it.

Attachment: 07-fixedpoint.patch
Description: Binary data

Follow-Ups:
- Re: [PATCH][ARM][5/n] Partial IT block deprecation in ARMv8 AArch32 - load/store multiple
  - From: Richard Earnshaw

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]