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[PATCH 6/6] rs6000: dot for ashiftrt
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: gcc-patches at gcc dot gnu dot org
- Cc: dje dot gcc at gmail dot com, Segher Boessenkool <segher at kernel dot crashing dot org>
- Date: Fri, 31 May 2013 14:28:11 -0700
- Subject: [PATCH 6/6] rs6000: dot for ashiftrt
- References: <14577e1c6b530d6f4feda94ba84896983b05513b dot 1370028541 dot git dot segher at kernel dot crashing dot org>
- References: <14577e1c6b530d6f4feda94ba84896983b05513b dot 1370028541 dot git dot segher at kernel dot crashing dot org>
Last for now: move ashiftrt to integer.mdm. Also allow the dot
of lshrsi3_imm in 64-bit mode, if the shift amount is more than 0.
2013-05-31 Segher Boessenkool <segher@kernel.crashing.org>
gcc/
* config/rs6000/rs6000.md (ashrsi3, ashrdi3_no_power,
ashrdisi3_noppc64be, ashrdi3, ashrdi3_internal1, ashrdi3_internal2,
ashrdi3_internal3): Delete.
* config/rs6000/integer.mdm (lshr<mode>3_imm): Add extra dot
condition.
(ashr<mode>3, ashr<mode>3_imm): New.
* config/rs6000/integer.md: Regenerate.
---
gcc/config/rs6000/integer.md | 164 +++++++++++++++++++++++++++++++++-
gcc/config/rs6000/integer.mdm | 20 ++++-
gcc/config/rs6000/rs6000.md | 201 ------------------------------------------
3 files changed, 179 insertions(+), 206 deletions(-)
diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md
index ce2c240..8da09df 100644
--- a/gcc/config/rs6000/integer.md
+++ b/gcc/config/rs6000/integer.md
@@ -280,7 +280,7 @@ (define_insn "*lshr<mode>3_imm_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
- && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)"
+ && ((<MODE>mode == Pmode || UINTVAL (operands[2])) && rs6000_gen_cell_microcode)"
"@
sr<wd>i. %0,%1,%2
#"
@@ -296,7 +296,7 @@ (define_split
(const_int 0)))
(clobber (match_scratch:GPR 0 ""))]
"((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
- && (<MODE>mode == Pmode && rs6000_gen_cell_microcode))
+ && ((<MODE>mode == Pmode || UINTVAL (operands[2])) && rs6000_gen_cell_microcode))
&& (reload_completed)"
[(set (match_dup 0)
(lshiftrt:GPR (match_dup 1)
@@ -316,7 +316,7 @@ (define_insn "*lshr<mode>3_imm_dot2"
(lshiftrt:GPR (match_dup 1)
(match_dup 2)))]
"(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
- && (<MODE>mode == Pmode && rs6000_gen_cell_microcode)"
+ && ((<MODE>mode == Pmode || UINTVAL (operands[2])) && rs6000_gen_cell_microcode)"
"@
sr<wd>i. %0,%1,%2
#"
@@ -334,7 +334,7 @@ (define_split
(lshiftrt:GPR (match_dup 1)
(match_dup 2)))]
"((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
- && (<MODE>mode == Pmode && rs6000_gen_cell_microcode))
+ && ((<MODE>mode == Pmode || UINTVAL (operands[2])) && rs6000_gen_cell_microcode))
&& (reload_completed)"
[(set (match_dup 0)
(lshiftrt:GPR (match_dup 1)
@@ -344,6 +344,162 @@ (define_split
(const_int 0)))]
"")
+(define_insn "ashr<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ ""
+ "sra<wd> %0,%1,%2"
+ [(set_attr "type" "var_shift_rotate")])
+
+(define_insn "*ashr<mode>3_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "rs6000_gen_cell_microcode"
+ "@
+ sra<wd>. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "var_shift_rotate")])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "gpc_reg_operand" ""))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 ""))]
+ "(rs6000_gen_cell_microcode)
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashr<mode>3_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "gpc_reg_operand" "r,r"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))]
+ "rs6000_gen_cell_microcode"
+ "@
+ sra<wd>. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "var_shift_rotate")])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "gpc_reg_operand" ""))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(rs6000_gen_cell_microcode)
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashr<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i")))]
+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+ "sra<wd>i %0,%1,%2"
+ [(set_attr "type" "shift")])
+
+(define_insn "*ashr<mode>3_imm_dot"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=r,r"))]
+ "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (rs6000_gen_cell_microcode)"
+ "@
+ sra<wd>i. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "shift")])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 ""))]
+ "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (rs6000_gen_cell_microcode))
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
+(define_insn "*ashr<mode>3_imm_dot2"
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+ (match_operand:SI 2 "const_int_operand" "i,i"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))]
+ "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (rs6000_gen_cell_microcode)"
+ "@
+ sra<wd>i. %0,%1,%2
+ #"
+ [(set_attr "length" "4,8")
+ (set_attr "dot" "yes,no")
+ (set_attr "type" "shift")])
+
+(define_split
+ [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
+ (compare:CC
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))]
+ "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode))
+ && (rs6000_gen_cell_microcode))
+ && (reload_completed)"
+ [(set (match_dup 0)
+ (ashiftrt:GPR (match_dup 1)
+ (match_dup 2)))
+ (set (match_dup 3)
+ (compare:CC (match_dup 0)
+ (const_int 0)))]
+ "")
+
; -- Logical instructions:
; andi., andis., ori, oris, xori, xoris
diff --git a/gcc/config/rs6000/integer.mdm b/gcc/config/rs6000/integer.mdm
index 96ea3e9..3edbc0b 100644
--- a/gcc/config/rs6000/integer.mdm
+++ b/gcc/config/rs6000/integer.mdm
@@ -60,10 +60,28 @@
(lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")))]
"UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "(<MODE>mode == Pmode || UINTVAL (operands[2])) && rs6000_gen_cell_microcode"
"sr<wd>i %0,%1,%2"
[(set_attr "type" "shift")])
+(define_dot_insn "ashr<mode>3"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
+ ""
+ "rs6000_gen_cell_microcode"
+ "sra<wd> %0,%1,%2"
+ [(set_attr "type" "var_shift_rotate")])
+
+(define_dot_insn "*ashr<mode>3_imm"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "i")))]
+ "UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+ "rs6000_gen_cell_microcode"
+ "sra<wd>i %0,%1,%2"
+ [(set_attr "type" "shift")])
+
; -- Logical instructions:
; andi., andis., ori, oris, xori, xoris
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8765340..fb074a7 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4620,16 +4620,6 @@ (define_split
(const_int 0)))]
"")
-(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- ""
- "@
- sraw %0,%1,%2
- srawi %0,%1,%h2"
- [(set_attr "type" "var_shift_rotate,shift")])
-
(define_insn "*ashrsi3_64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(sign_extend:DI
@@ -4640,51 +4630,6 @@ (define_insn "*ashrsi3_64"
sraw %0,%1,%2
srawi %0,%1,%h2"
[(set_attr "type" "var_shift_rotate,shift")])
-
-(define_insn ""
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r,r,r"))]
- ""
- "@
- sraw. %3,%1,%2
- srawi. %3,%1,%h2
- #
- #"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "reload_completed"
- [(set (match_dup 3)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn ""
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))]
- ""
- "@
- sraw. %0,%1,%2
- srawi. %0,%1,%h2
- #
- #"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
;; Builtins to replace a division to generate FRE reciprocal estimate
;; instructions and the necessary fixup instructions
@@ -4725,21 +4670,6 @@ (define_expand "rsqrt<mode>2"
DONE;
})
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "reload_completed"
- [(set (match_dup 0)
- (ashiftrt:SI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
;; Floating-point insns, excluding normal data motion.
;;
;; PowerPC has a full set of single-precision floating point instructions.
@@ -6490,49 +6420,6 @@ (define_insn "umulsi3_highpart"
""
"mulhwu %0,%1,%2"
[(set_attr "type" "imul")])
-
-;; Shift by a variable amount is too complex to be worth open-coding. We
-;; just handle shifts by constants.
-(define_insn "ashrdi3_no_power"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "M,i")))]
- "!TARGET_POWERPC64"
- "*
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
- else
- return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
- case 1:
- if (WORDS_BIG_ENDIAN)
- return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
- else
- return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
- }
-}"
- [(set_attr "type" "two,three")
- (set_attr "length" "8,12")])
-
-(define_insn "*ashrdisi3_noppc64be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (const_int 32)) 4))]
- "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]))
- return \"\";
- else
- return \"mr %0,%1\";
-}"
- [(set_attr "length" "4")])
-
;; PowerPC64 DImode operations.
@@ -7454,94 +7341,6 @@ (define_split
(const_int 0)))]
"")
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" "")))]
- ""
- "
-{
- if (TARGET_POWERPC64)
- ;
- else if (GET_CODE (operands[2]) == CONST_INT)
- {
- emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
- DONE;
- }
- else
- FAIL;
-}")
-
-(define_insn "*ashrdi3_internal1"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
- "TARGET_POWERPC64"
- "@
- srad %0,%1,%2
- sradi %0,%1,%H2"
- [(set_attr "type" "var_shift_rotate,shift")])
-
-(define_insn "*ashrdi3_internal2"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r,r,r"))]
- "TARGET_64BIT"
- "@
- srad. %3,%1,%2
- sradi. %3,%1,%H2
- #
- #"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 3)
- (ashiftrt:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*ashrdi3_internal3"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
- (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT"
- "@
- srad. %0,%1,%2
- sradi. %0,%1,%H2
- #
- #"
- [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
- (set_attr "length" "4,4,8,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
- (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && reload_completed"
- [(set (match_dup 0)
- (ashiftrt:DI (match_dup 1) (match_dup 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_expand "anddi3"
[(parallel
[(set (match_operand:DI 0 "gpc_reg_operand" "")
--
1.8.1.4