Hi all,
This patch improves code generation for DImode bitwise IOR operations
for arm. The expander can now handle immediate values and the
define_insn is changed to an insn_and_split.
The NEON version is merged with the scalar version.
For code:
unsigned long long or64 (unsigned long long input)
{
return input | 0x200000004ULL;
}
we now generate:
orr r0, r0, #4
orr r1, r1, #2
Instead of:
mov r2, #4
mov r3, #2
orr r0, r0, r2
orr r1, r1, r3
Regtested arm-none-eabi on qemu and bootstrapped on a Cortex-A15.
gcc.target/arm/neon-for-64bits-2.c scan-assembler-times vorr 1 starts
failing with this patch because now the compiler chooses not to generate
the NEON version for that testcase.
Previously, it would generate the NEON form because the "r" constraints
were suppressed explicitly with '?', but we'd prefer to trust the
optimisers to make the correct decision, therefore I didn't
copy over the '?'.
Ok for trunk?
Thanks,
Kyrill
gcc/
2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/56315
* config/arm/arm.c (const_ok_for_dimode_op): Handle IOR.
* config/arm/arm.md (*iordi3_insn): Change to insn_and_split.
* config/arm/neon.md (iordi3_neon): Remove.
(neon_vorr<mode>): Generate iordi3 instead of iordi3_neon.
* config/arm/predicates.md (imm_for_neon_logic_operand):
Move to earlier in the file.
(neon_logic_op2): Likewise.
(arm_iordi_operand_neon): New predicate.
gcc/testsuite/
2013-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/56315
* gcc.target/arm/iordi3-opt.c: New test.