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This is the final set of patches that I have available right now. We will be doing additional patches over the summer. The primary thing in this patch is to add support for load fusion in the power8. Power8 has two types of fusion: addi <a>,<b>,<const> lxvd2x <va>,<b>,<c> and: addis <a>,<b>,<const-hi> ld <a>,<const-lo>(<a>) These instructions must be adjacent to each other, and in the case of fusion in loading GPRs, the register being loaded must be the base register to load from it. In this patch, I added peepholes to cover this case. In the future, I plan on reworking the problem by being more liberal in what addresses are allowed before reload/lra, and in lra, generate these forms. However, these peepholes do help find fusion cases. I also added two switches (-mlra and -mconstrain-regs) that were used in converting the powerpc port to use the LRA register allocator. Note, at the present time, Vlad and I are going back on forth on additional things needed for LRA. This patch bootstraps and has no regressions in the test suite. Is it ok to check in after the previous 7 patches have been applied? FWIW, patches 1-2 that were approved have now been checked in. 2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/predicates.md (fusion_gpr_addis): New predicates to support power8 load fusion. (fusion_gpr_mem_load): Likewise. * config/rs6000/rs6000-modes.def (PTImode): Update a comment. * config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New declarations for power8 load fusion. (emit_fusion_gpr_load): Likewise. * config/rs6000/rs6000.opt (-mlra): New undocumented switch to turn on using the LRA register allocator. (-mconstrain-regs): New undocumented switch to constrain non-integer values from being loaded into the LR or CTR registers. * config/rs6000/rs6000.c (TARGET_LRA_P): If -mlra, turn on using the LRA register allocator. (rs6000_lra_p): Likewise. (rs6000_hard_regno_mode_ok): Allow DI/DD/SF/SD modes in altivec registers if power8. If -mconstrain-regs, only allow int modes into LR, CTR, and special purpose registers. (rs6000_debug_reg_global): Print -mlra, -mconstrain-regs status if debugging. (rs6000_init_hard_regno_mode_ok): Mark that SFmode can use Altivec registers in the future. (rs6000_option_override_internal): If tuning for power8, turn on fusion mode by default. Turn on sign extending fusion mode if normal fusion mode is on, and we are at -O2 or -O3. (rs6000_opt_masks): Add -mlra, -mconstrain-regs. (fusion_gpr_load_p): New function, return true if we can fuse an addis instruction with a dependent load to a GPR. (emit_fusion_gpr_load): Emit the instructions for power8 load fusion to GPRs. * config/rs6000/vsx.md (VSX load fusion peepholes): Add peepholes to fuse together an addi instruction with a VSX load instruction. * config/rs6000/rs6000.md (GPR load fusion peepholes): Add peepholes to fuse an addis instruction with a load to a GPR base register, if the addis instruction is dead after the load, by using the register to be loaded for the addis. If we are supporting sign extending fusions, convert sign extending loads to zero extending loads and an explicit sign extension. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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