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Re: [PATCH, AArch64] Testcases for ANDS instruction
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Ian Bolton <ian dot bolton at arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 26 Apr 2013 14:25:53 +0100
- Subject: Re: [PATCH, AArch64] Testcases for ANDS instruction
- References: <000001ce427d$3e8f7fa0$bbae7ee0$ at bolton@arm.com>
On 26/04/13 13:54, Ian Bolton wrote:
I made some testcases to go with my implementation of ANDS in the backend,
but Naveen Hurugalawadi got the ANDS patterns in before me!
I'm now just left with the testcases, but they are still worth adding, so
here they are.
Tests are working correctly as of current trunk.
OK to commit?
Cheers,
Ian
2013-04-26 Ian Bolton <ian.bolton@arm.com>
* gcc.target/aarch64/ands.c: New test.
* gcc.target/aarch64/ands2.c: Likewise
aarch64-ands-tests-svn-patch-v2.txt
Index: gcc/testsuite/gcc.target/aarch64/ands2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/ands2.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/ands2.c (revision 0)
@@ -0,0 +1,157 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
This rule
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
Will match anything that this rule
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
matches (though not vice versa).
Similarly for the x register variants.
R.