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Re: [PATCH, AARCH64] Fix unrecognizable insn issue
- From: Marcus Shawcroft <marcus dot shawcroft at gmail dot com>
- To: "zhenqiang dot chen at linaro dot org" <zhenqiang dot chen at linaro dot org>
- Cc: James Greenhalgh <james dot greenhalgh at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, "pinskia at gmail dot com" <pinskia at gmail dot com>, Richard Earnshaw <rearnsha at arm dot com>
- Date: Wed, 10 Apr 2013 11:48:45 +0100
- Subject: Re: [PATCH, AARCH64] Fix unrecognizable insn issue
- References: <CACgzC7ADK2m2u8P9SOvjVB+=wsV2UwRHsRWvAWDtxhyao55AAg at mail dot gmail dot com> <1365589912-3344-1-git-send-email-james dot greenhalgh at arm dot com> <5165423E dot 1040900 at arm dot com>
Zhenqiang, Does Jame's patch fix your test case?
/Marcus
On 10 April 2013 11:43, Richard Earnshaw <rearnsha@arm.com> wrote:
> On 10/04/13 11:31, James Greenhalgh wrote:
>>
>>
>>> -----Original Message-----
>>> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
>>> owner@gcc.gnu.org] On Behalf Of Zhenqiang Chen
>>> Sent: 10 April 2013 09:02
>>> To: gcc-patches@gcc.gnu.org
>>> Cc: Marcus Shawcroft
>>> Subject: [PATCH, AARCH64] Fix unrecognizable insn issue
>>>
>>> Hi,
>>>
>>> During expand, function aarch64_vcond_internal inverses some CMP, e.g.
>>>
>>> a LE b -> b GE a
>>>
>>> But if "b" is "CONST0_RTX", "b GE a" will be an illegal insn.
>>
>>
>> Yes it will. We should not be swapping the comparison in these cases.
>>
>>>
>>> Refer https://bugs.launchpad.net/linaro-toolchain-binaries/+bug/1163942
>>> for detail about the issue.
>>>
>>> The patch is to make "b" a register when inversing LE.
>>
>>
>> This patch is too restrictive. There is an `fcmle v0.2d #0` form which we
>> should be generating when we can. Also, you are only fixing one
>> problematic
>> case where there are a few.
>>
>> I don't have access to your reproducer, so I can't be certain this patch
>> is correct - I have created my own reproducer and added it in with
>> the other vect-fcm tests.
>>
>> Thorough regression tests are ongoing for this patch, but it
>> passes aarch64.exp and vect.exp with no regressions.
>>
>> Thanks,
>> James
>>
>> ---
>> gcc/
>>
>> 2013-04-10 James Greenhalgh <james.greenhalgh@arm.com>
>>
>> * config/aarch64/aarch64-simd.md (aarch64_vcond_internal): Fix
>> floating-point vector comparisons against 0.
>>
>> gcc/testsuite/
>>
>> 2013-04-10 James Greenhalgh <james.greenhalgh@arm.com>
>>
>> * gcc.target/aarch64/vect-fcm.x: Add check for zero forms of
>> inverse operands.
>> * gcc.target/aarch64/vect-fcm-eq-d.c: Check that new zero form
>> loop is vectorized.
>> * gcc.target/aarch64/vect-fcm-eq-f.c: Likewise.
>> * gcc.target/aarch64/vect-fcm-ge-d.c: Check that new zero form
>> loop is vectorized and that the correct instruction is generated.
>> * gcc.target/aarch64/vect-fcm-ge-f.c: Likewise.
>> * gcc.target/aarch64/vect-fcm-gt-d.c: Likewise.
>> * gcc.target/aarch64/vect-fcm-gt-f.c: Likewise.
>>
>>
>
> OK.
>
> R.
>
>