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Re: [AArch64] Bitwise adds and subs instructions with shift

From: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
To: "Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at caviumnetworks dot com>
Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Ian Bolton <Ian dot Bolton at arm dot com>
Date: Thu, 28 Mar 2013 18:36:47 +0000
Subject: Re: [AArch64] Bitwise adds and subs instructions with shift
References: <F3068DEED1A463459E0887A091B15493123546F4 at BY2PRD0710MB364 dot namprd07 dot prod dot outlook dot com>

Hi,

I'm not sure how good the coverage is from these test cases
On 26/03/13 11:42, Hurugalawadi, Naveen wrote:

  (define_insn "*add<mode>3_compare0"
    [(set (reg:CC_NZ CC_REGNUM)
  	(compare:CC_NZ
-	 (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+	 (plus:GPI (match_operand:GPI 1 "register_operand" "%rk,rk")
  		   (match_operand:GPI 2 "aarch64_plus_operand" "rI,J"))


SP is not valid for ADDS shifted register form.

  (define_insn "*addsi3_compare0_uxtw"
    [(set (reg:CC_NZ CC_REGNUM)
  	(compare:CC_NZ
-	 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
+	 (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk")
  		  (match_operand:SI 2 "aarch64_plus_operand" "rI,J"))


Likewise.

+(define_insn "*adds_<shift>_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:GPI (ASHIFT:GPI
+		    (match_operand:GPI 1 "register_operand" "r")
+		    (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+		   (match_operand:GPI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
+		  (match_dup 3)))]
+  ""
+  "adds\\t%<w>0, %<w>3, %<w>1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")


alus_shift

Looking at the output from the tests supplied below, I don;t think thispattern is tested.

+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*adds_<shift>_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:SI (ASHIFT:SI
+		   (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+		  (match_operand:SI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (plus:SI (ASHIFT:SI (match_dup 1) (match_dup 2))
+				 (match_dup 3))))]
+  ""
+  "adds\\t%w0, %w3, %w1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")


alus_shift

Likewise, does the test case below hit this pattern?

+(define_insn "*adds_mul_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:GPI (mult:GPI
+		    (match_operand:GPI 1 "register_operand" "r")
+		    (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
+		   (match_operand:GPI 3 "register_operand" "rk"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
+		  (match_dup 3)))]
+  ""
+  "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")


alus_shift

+;; zero_extend version of above
+(define_insn "*adds_mul_imm_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:SI (mult:SI
+		   (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:QI 2 "aarch64_pwr_2_si" "n"))
+		  (match_operand:SI 3 "register_operand" "rk"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (plus:SI (mult:SI (match_dup 1) (match_dup 2))
+				 (match_dup 3))))]
+  ""
+  "adds\\t%w0, %w3, %w1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]


alus_shift

Does this one have test coverage?

+
+(define_insn "*subs_<shift>_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+		    (ASHIFT:GPI
+		     (match_operand:GPI 2 "register_operand" "r")
+		     (match_operand:QI 3 "aarch64_shift_imm_<mode>" "n")))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(minus:GPI (match_dup 1)
+		   (ASHIFT:GPI (match_dup 2) (match_dup 3))))]
+  ""
+  "subs\\t%<w>0, %<w>1, %<w>2, <shift> %3"
+  [(set_attr "v8type" "alu_shift")


alus_shift

Does this one have test coverage?

+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*subs_<shift>_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:SI (match_operand:SI 1 "register_operand" "r")
+		   (ASHIFT:SI
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:QI 3 "aarch64_shift_imm_si" "n")))
+	(const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (minus:SI (match_dup 1)
+				  (ASHIFT:SI (match_dup 2) (match_dup 3)))))]
+  ""
+  "subs\\t%w0, %w1, %w2, <shift> %3"
+  [(set_attr "v8type" "alu_shift")


alus_shift
Does this one have test coverage?

+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*subs_mul_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
+		    (mult:GPI
+		     (match_operand:GPI 2 "register_operand" "r")
+		     (match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(minus:GPI (match_dup 1)
+		   (mult:GPI (match_dup 2) (match_dup 3))))]
+  ""
+  "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
+  [(set_attr "v8type" "alu_shift")


alus_shift

+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*subs_mul_imm_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:SI (match_operand:SI 1 "register_operand" "rk")
+		   (mult:SI
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:QI 3 "aarch64_pwr_2_si" "n")))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (minus:SI (match_dup 1)
+				  (mult:SI (match_dup 2) (match_dup 3)))))]
+  ""
+  "subs\\t%w0, %w1, %w2, lsl %p3"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]


alus_shift
Does this one have test coverage?

+)
+
  (define_insn "*add<mode>3nr_compare0"
    [(set (reg:CC_NZ CC_REGNUM)
  	(compare:CC_NZ
@@ -1633,7 +1773,7 @@

  (define_insn "*sub<mode>3_compare0"
    [(set (reg:CC_NZ CC_REGNUM)
-	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
  				  (match_operand:GPI 2 "register_operand" "r"))


subs shifted register does not permit SP.

  		       (const_int 0)))
     (set (match_operand:GPI 0 "register_operand" "=r")
@@ -1647,7 +1787,7 @@
  ;; zero_extend version of above
  (define_insn "*subsi3_compare0_uxtw"
    [(set (reg:CC_NZ CC_REGNUM)
-	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "r")
+	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "rk")
  				 (match_operand:SI 2 "register_operand" "r"))


Likewise.


Cheers
/Marcus

References:
- [AArch64] Bitwise adds and subs instructions with shift
  - From: Hurugalawadi, Naveen

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