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Re: [PING^1] [AArch64] Implement Bitwise AND and Set Flags
- From: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- To: "Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at caviumnetworks dot com>
- Cc: Ian Bolton <ian dot bolton at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 28 Mar 2013 17:22:51 +0000
- Subject: Re: [PING^1] [AArch64] Implement Bitwise AND and Set Flags
- References: <F3068DEED1A463459E0887A091B154933DB662 at BY2PRD0710MB364 dot namprd07 dot prod dot outlook dot com>,<000c01ce2180$0864b030$192e1090$ at bolton@arm.com>,<F3068DEED1A463459E0887A091B1549312354668 at BY2PRD0710MB364 dot namprd07 dot prod dot outlook dot com> <F3068DEED1A463459E0887A091B15493123546E6 at BY2PRD0710MB364 dot namprd07 dot prod dot outlook dot com>
On 26/03/13 11:35, Hurugalawadi, Naveen wrote:
Hi,
>>Can we split them into two different patches. Just and in one
Thanks for reviewing the patch. I have split the patches for "and"
separately as per your suggestion.
Thanks, I've adjusted the patch to use the SHIFT iterator instead of
ASHIFT and committed as attached.
Ian, has a BICS implementation to follow which will include his testcase
as previously posted for both ANDS and BICS.
/Marcus
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ca94d70..4f04081 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2467,6 +2467,69 @@
[(set_attr "v8type" "logic,logic_imm")
(set_attr "mode" "SI")])
+(define_insn "*and<mode>3_compare0"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+ (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r,r")
+ (and:GPI (match_dup 1) (match_dup 2)))]
+ ""
+ "ands\\t%<w>0, %<w>1, %<w>2"
+ [(set_attr "v8type" "logics,logics_imm")
+ (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*andsi3_compare0_uxtw"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:SI (match_operand:SI 1 "register_operand" "%r,r")
+ (match_operand:SI 2 "aarch64_logical_operand" "r,K"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r,r")
+ (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+ ""
+ "ands\\t%w0, %w1, %w2"
+ [(set_attr "v8type" "logics,logics_imm")
+ (set_attr "mode" "SI")]
+)
+
+(define_insn "*and_<SHIFT:optab><mode>3_compare0"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (SHIFT:GPI
+ (match_operand:GPI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+ (match_operand:GPI 3 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r")
+ (and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ ""
+ "ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
+ [(set_attr "v8type" "logics_shift")
+ (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*and_<SHIFT:optab>si3_compare0_uxtw"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:SI (SHIFT:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+ (match_operand:SI 3 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (and:SI (SHIFT:SI (match_dup 1) (match_dup 2))
+ (match_dup 3))))]
+ ""
+ "ands\\t%w0, %w3, %w1, <SHIFT:shift> %2"
+ [(set_attr "v8type" "logics_shift")
+ (set_attr "mode" "SI")]
+)
+
(define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (SHIFT:GPI