RE: [PING^1] [AArch64] Implement Bitwise AND and Set Flags

["Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at caviumnetworks dot com>]

Hi,

>> Can we split them into two different patches.  Just and in one

Thanks for reviewing the patch. I have split the patches for "and"
separately as per your suggestion.

There were some doubts regarding the addressing modes supported by 
these instructions.
The only source that could be referred was the AARCH64 assembler.
Hence, these modifications are implemented as per the assembler.
Please let me know if there should be any modifications.

>> the second "set" in each pattern should have the "=r,rk" constraint
>> rather than just "=r,r".
If the destination operand is stack register, assembler generates error
as follows:-
Error: operand 1 should be an integer register -- `ands sp,x0,x1' 
The ands instruction does not support sp in any of the operand as per
the assembler. 

>> I've attached a patch that provides more thorough test cases,
>> including execute ones. 
Thanks for the testcase. They were added in the testsuite and run to
check the implementation. However, the testcase had shift operations in
them. Hence, the pattern for shift are added in the patch.

Please review the same and let me know if there should be any 
modifications in the patch.

Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). 

Thanks,
Naveen

gcc/

2013-03-26   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.
	(*andsi3_compare0_si_uxtw): New pattern.
	(*ands_<shift>_<mode>): New pattern.
	(*ands_<shift>_si_uxtw): New pattern.

gcc/testsuite/

2013-03-26   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/ands.c: New.

--- gcc/config/aarch64/aarch64.md	2013-03-26 12:51:12.180448029 +0530
+++ gcc/gcc/config/aarch64/aarch64.md	2013-03-26 16:54:28.932943068 +0530
@@ -2433,6 +2433,70 @@
   [(set_attr "v8type" "logic,logic_imm")
    (set_attr "mode" "SI")])
 
+(define_insn "*and<mode>3_compare0"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+		  (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r,r")
+	(and:GPI (match_dup 1) (match_dup 2)))]
+  ""
+  "ands\\t%<w>0, %<w>1, %<w>2"
+  [(set_attr "v8type" "logic,logic_imm")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*andsi3_compare0_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (and:SI (match_operand:SI 1 "register_operand" "%r,r")
+		 (match_operand:SI 2 "aarch64_logical_operand" "r,K"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
+  ""
+  "ands\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "logic,logic_imm")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*ands_<shift>_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (and:GPI (ASHIFT:GPI
+		   (match_operand:GPI 1 "register_operand" "r")
+		   (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+		  (match_operand:GPI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(and:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
+		 (match_dup 3)))]
+  ""
+  "ands\\t%<w>0, %<w>3, %<w>1, <shift> %2"
+  [(set_attr "v8type" "logics_shift")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*ands_<shift>_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (and:SI (ASHIFT:SI
+		  (match_operand:SI 1 "register_operand" "r")
+		  (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+		 (match_operand:SI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (and:SI (ASHIFT:SI (match_dup 1) (match_dup 2))
+				(match_dup 3))))]
+  ""
+  "ands\\t%w0, %w3, %w1, <shift> %2"
+  [(set_attr "v8type" "logics_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 	(LOGICAL:GPI (SHIFT:GPI
--- gcc/testsuite/gcc.target/aarch64/ands.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/ands.c	2013-03-26 16:52:28.504938984 +0530
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+  int l = x & y;
+  if (l == 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]" } } */
+  z = l ;
+  return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+  s64 l = x & y;
+  if (l < 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]" } } */
+  zz = l ;
+  return 25;
+}