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Re: extend fwprop optimization
- From: Wei Mi <wmi at google dot com>
- To: Richard Biener <richard dot guenther at gmail dot com>
- Cc: Steven Bosscher <stevenb dot gcc at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, David Li <davidxl at google dot com>, Uros Bizjak <ubizjak at gmail dot com>
- Date: Mon, 25 Mar 2013 10:33:31 -0700
- Subject: Re: extend fwprop optimization
- References: <CA+4CFy4N5+g0XVJ4vDtGyqHOgj15t3vDiiF0A8_1H9hKNZ+LuQ at mail dot gmail dot com> <CABu31nMvJnvWoj-xA-YkOeH5XLgj+8OLjALyxE+pMaA=s91_KA at mail dot gmail dot com> <CA+4CFy6q-HXCJ3jPQwGzV_beysTdEV-GVsY=0oFLbL-iDVaSbQ at mail dot gmail dot com> <CABu31nOAuZ16eQS+8fq=bntXXfzfzHT7aCZh_vnJG4xh45Yccg at mail dot gmail dot com> <CA+4CFy5++86xq8q7_4x-YuOCHSrpsZ4QST1J6KFK_X_EjxRh+A at mail dot gmail dot com> <CABu31nPB3t+b61fSndgbFD-Ps4SXo62872f2cOyRBOi0nW22ig at mail dot gmail dot com> <CA+4CFy6thk60J=4O626nFKC9t9ivYyg9jPtMHcBWGdM=t49Ubg at mail dot gmail dot com> <CA+4CFy5GkeRqe=9Q8tc688UiFXpe2vFS-QjKUpbuWLCRHV8coA at mail dot gmail dot com> <CABu31nN64RUCC8TBjUEunUMDcu0BAuV7+_JT2aogbJ4uybiRFw at mail dot gmail dot com> <CA+4CFy5fYWHAHWgzL+SNBm3H+LophqSEo3LMwqKgW2FCej2A9Q at mail dot gmail dot com> <CABu31nOtV85auTQa8mGFZ6Lnz81VQPbgoeXGLsu58PB0nLJ9JQ at mail dot gmail dot com> <CA+4CFy5fYFpUK3FmmWoVTrSxBamGhBy=+_dQEa24TSVLY62SiQ at mail dot gmail dot com> <CA+4CFy5qgj_vxOxouauPvwAWA77sWe6wmrN9MW90fOZVhS7KnQ at mail dot gmail dot com> <CAFiYyc2oGc4DArocxSdYbscDbmrsLWFgqJPWCfUD5pK5C6o+GQ at mail dot gmail dot com> <CA+4CFy4=kGL8b0AHfu=U+hTmYyhuUQEZKOMH0mRQ8u-GaL4BOg at mail dot gmail dot com>
> I am trying to figure out a way not to lose the opportunity when shift
> truncation is not combined in a bit test pattern. Can we keep the
> explicit truncation in RTL, but generate truncation code in assembly?
> Then only shift truncation which not combined in a bit test
> pattershift truncationn will happen.
>
> (define_insn "*<shift_insn_and><mode>"
> [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
> (any_shiftrt:SWI48
> (match_operand:SWI48 1 "nonimmediate_operand" "0")
> (subreg:QI
> (and:SI
> (match_operand:SI 2 "nonimmediate_operand" "c")
> (match_operand:SI 3 "const_int_operand" "n")) 0)))
> (clobber (reg:CC FLAGS_REG))]
> "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
> {
> if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
> == GET_MODE_BITSIZE (<MODE>mode)-1)
> return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}";
> else
> "shift\t{%2, %0|%0, %2}";
> }
Sorry, rectify a mistake:
{
if ((INTVAL (operands[3]) & (GET_MODE_BITSIZE (<MODE>mode)-1))
== GET_MODE_BITSIZE (<MODE>mode)-1)
return "shift\t{%2, %0|%0, %2}";
else
return "and\t{%3, %2|%2, %3}\n\r shift\t{%b2, %0|%0, %b2}";
}
Thanks,
Wei.