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Re: [PATCH] PowerPC merge TD/TF moves
- From: David Edelsohn <dje dot gcc at gmail dot com>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, gcc-patches at gcc dot gnu dot org
- Date: Thu, 7 Mar 2013 20:45:10 -0500
- Subject: Re: [PATCH] PowerPC merge TD/TF moves
- References: <20130130225005.GA4615@ibm-tiger.the-meissners.org>
On Wed, Jan 30, 2013 at 5:50 PM, Michael Meissner
> This patch like the previous 2 pages combines the decimal and binary floating
> point moves, this time for 128-bit floating point.
> In doing this patch, I discovered that I left out the code in the previous
> patch to enable the wg constraint to enable -mcpu=power6x to utilize the direct
> move instructions. So, I added the code in this patch, and also created a test
> to make sure that direct moves are generated in the future.
> I also added the reload helper for DDmode to rs6000_vector_reload that was
> missed in the last patch. This was harmless, since that is only used with an
> undocumented debug switch. Hopefully sometime in the future, I will scalar
> floating point to be able to be loaded in the upper 32 VSX registers that are
> overlaid over the Altivec registers.
> Like the previous 2 patches, I've bootstrapped this, and ran make check with no
> regressions. Is it ok to apply when GCC 4.9 opens up?
> I have one more patch in the insn combination to post, combining movdi on
> systems with normal floating point and with the power6 direct move
Which of these sets of patches adjusts and updates
rs6000_register_move_cost for -mfpgpr and for VSRs and FPRs sharing
the same register file?