[AArch64] Implement Bitwise AND and Set Flags

["Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at caviumnetworks dot com>]

Hi,

Please find attached the patch that implements Bitwise AND and Set
Flags instruction for aarch64 target.
The patch adds a testcase ands.c which is similar to the adds.c.

Please review the patch and let me know if there should be any
modifications?

Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). 

Thanks,
Naveen.H.S

gcc/

2013-01-29   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.
	(*andsi3_compare0_uxtw): New pattern.

gcc/testsuite/

2013-01-29   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/ands.c: New.

--- gcc/config/aarch64/aarch64.md	2013-01-29 12:27:37.289475066 +0530
+++ gcc/config/aarch64/aarch64.md	2013-01-29 11:43:06.693434952 +0530
@@ -2433,6 +2433,35 @@
   [(set_attr "v8type" "logic,logic_imm")
    (set_attr "mode" "SI")])
 
+(define_insn "*and<mode>3_compare0"
+  [(set (reg:CC CC_REGNUM)
+	(compare:CC
+	 (and:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+		  (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r,r")
+	(and:GPI (match_dup 1) (match_dup 2)))]
+  ""
+  "ands\\t%<w>0, %<w>1, %<w>2"
+  [(set_attr "v8type" "logic,logic_imm")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*andsi3_compare0_uxtw"
+  [(set (reg:CC CC_REGNUM)
+	(compare:CC
+	 (and:SI (match_operand:SI 1 "register_operand" "%r,r")
+		 (match_operand:SI 2 "aarch64_logical_operand" "r,K"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+  ""
+  "ands\\t%w0, %w1, %w2"
+  [(set_attr "v8type" "logic,logic_imm")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
 	(LOGICAL:GPI (SHIFT:GPI
--- gcc/testsuite/gcc.target/aarch64/ands.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/ands.c	2013-01-29 12:29:02.001476339 +0530
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+  int l = x & y;
+  if (l == 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]" } } */
+  z = l ;
+  return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+  s64 l = x & y;
+  if (l < 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]" } } */
+  zz = l ;
+  return 25;
+}