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RE: Ping: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1
- From: "Bin Cheng" <bin dot cheng at arm dot com>
- To: "Richard Earnshaw" <Richard dot Earnshaw at arm dot com>
- Cc: "'Richard Sandiford'" <rdsandiford at googlemail dot com>, "Ramana Radhakrishnan" <Ramana dot Radhakrishnan at arm dot com>, <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 6 Sep 2012 16:33:23 +0800
- Subject: RE: Ping: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1
- References: <005001cd793a$4e8956e0$eb9c04a0$@cheng@arm.com> <5045d229.8208b40a.1602.ffffde72SMTPIN_ADDED@mx.google.com> <87627t5tll.fsf@talisman.home> <003c01cd8bf2$3dd61840$b98248c0$@cheng@arm.com> <50485E7F.2060302@arm.com>
> >
> > Yes, it may be feasible to rewrite the instruction in machine reorg
> > pass, rather than peephole2. But that need bigger change in ARM back
end.
> > Hi Ramana, Richard, what's your opinion on this?
> >
> > Thanks very much.
> >
> >
>
> I side with Richard on this one. The mid-end should only have to deal
with
> RTL that's in canonical form.
>
So how about rewrite mov insn into sub in machine reorg pass and remove the
current peeophole2 codes?
Thanks