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Fix PR rtl-optimization/54369
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 2 Sep 2012 12:38:35 +0200
- Subject: Fix PR rtl-optimization/54369
This is a wrong code bug at -O2 reported for MIPS and caused by the discrepancy
between the natural placement of barriers in the RTL stream and the placement
expected by the dbr pass (actually by the delete_related_insns machinery).
The MIPS port invokes the dbr pass from its own reorg pass and the prerequisite
for the placement of barriers isn't fulfilled in this case. Ironically enough,
Richard S. remarked that the SPARC port is plagued by the same problem when its
own reorg pass is activated (but that's almost never the case for SPARC).
Tested by Steve on MIPS and me on SPARC, approved by Richard for the MIPS part
and applied on all active branches.
2012-09-02 Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/54369
* config/mips/mips.c (mips_reorg): Invoke cleanup_barriers before
calling dbr_schedule.
* config/sparc/sparc.c (sparc_reorg): Likewise.
--
Eric Botcazou
Index: config/sparc/sparc.c
===================================================================
--- config/sparc/sparc.c (revision 190664)
+++ config/sparc/sparc.c (working copy)
@@ -10691,7 +10691,10 @@ sparc_reorg (void)
/* We need to have the (essentially) final form of the insn stream in order
to properly detect the various hazards. Run delay slot scheduling. */
if (optimize > 0 && flag_delayed_branch)
- dbr_schedule (get_insns ());
+ {
+ cleanup_barriers ();
+ dbr_schedule (get_insns ());
+ }
/* Now look for specific patterns in the insn stream. */
for (insn = get_insns (); insn; insn = next)
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c (revision 190664)
+++ config/mips/mips.c (working copy)
@@ -15647,7 +15647,10 @@ mips_reorg (void)
}
if (optimize > 0 && flag_delayed_branch)
- dbr_schedule (get_insns ());
+ {
+ cleanup_barriers ();
+ dbr_schedule (get_insns ());
+ }
mips_reorg_process_insns ();
if (!TARGET_MIPS16
&& TARGET_EXPLICIT_RELOCS