[PATCH, i386]: Fix PR 46254, reload failure with -fpic -mcmodel={medium|large} and __sync_val_compare_and_swap

[Uros Bizjak <ubizjak at gmail dot com>]

Hello!

Attached patch fixes PR 46254. The problem was, that PIC code models,
different than small PIC still consume %rbx, even in 64bit mode. The
patch fixes this by enhancing atomic_compare_and_swap<dwi>_doubleword,
so the same macroized pattern now handles PIC and non-PIC compilations
for 32bit and 64bit  targets.

The patch introduces "fake early clobber" and penalized "r"
constraint. The clobber is not that "fake", since from now on, it also
prevents address registers (in addition to ecx register) to be
allocate as an early-clobbered temporary. Not only esi and edi can be
allocated now, but also ebp for 32bit targets or other REX registers
for 64bit targets can be used as temporaries for cmpxchg8, resp.
cmpxchg16.

2012-08-27  Uros Bizjak  <ubizjak@gmail.com>

	PR target/46254
	* config/i386/predicates.md (cmpxchg8b_pic_memory_operand): Return
	true for TARGET_64BIT or !flag_pic.
	* config/i386/sync.md (*atomic_compare_and_swap_doubledi_pic): Remove.
	(atomic_compare_and_swap_double<mode>): Change operand 2 predicate
	to cmpxchg8b_pic_memory_operand.  Use DWIH mode iterator.
	Add insn constraint.  Conditionally emit xchg asm insns.
	(atomic_compare_and_swap<mode>): Update calls.  Check only
	cmpxchg8b_pic_memory_operand in memory address fixup.
	(DCASMODE): Remove.
	(CASHMODE): Rename from DCASHMODE.
	(doublemodesuffix): Update modes.
	(regprefix): New mode attribute.

	(unspecv) <UNSPECV_CMPXCHG_{1,2,3,4}>: Remove.
	<UNSPECV_CMPXCHG>: New constant.
	(atomic_compare_and_swap<mode>_1): Rename from
	atomic_compare_and_swap_single<mode>.  Update calls and
	unspec_volatile constants.
	(atomic_compare_and_swap<mode>_doubleword): Rename from
	atomic_compare_and_swap_double<mode>.  Update calls and
	unspec_volatile constants.

testsuite/ChangeLog:

2012-08-27  Uros Bizjak  <ubizjak@gmail.com>

	PR target/46254
	* gcc.target/i386/pr46254.c: New test.

Patch was regression tested on x86_64-pc-linux-gnu {,-m32} and
committed to mainline SVN.

While not a regression (the testcase never worked), it is possible for
unpatched gcc to clobber address register in 32bit PIC mode. If there
are no objections, I plan to backport the patch to 4.7 branch.

Uros.

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