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[PATCH] Improve andq $0xffffffff, %reg handling (PR target/53110)
- From: Jakub Jelinek <jakub at redhat dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>, Richard Henderson <rth at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Wed, 25 Apr 2012 21:14:53 +0200
- Subject: [PATCH] Improve andq $0xffffffff, %reg handling (PR target/53110)
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
Hi!
We have a splitter for reg1 = reg2 & 0xffffffff, but only if regnums
are different. But movl %edi, %edi is a cheaper variant of
andq $0xffffffff, %rdi even with the same register and doesn't clobber
flags, so this patch attempts to expand it as a zero extension early.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2012-04-25 Jakub Jelinek <jakub@redhat.com>
PR target/53110
* config/i386/i386.md (and<mode>3): For andq $0xffffffff, reg
instead expand it as zero extension.
--- gcc/config/i386/i386.md.jj 2012-04-25 12:14:54.000000000 +0200
+++ gcc/config/i386/i386.md 2012-04-25 14:50:48.708925963 +0200
@@ -7694,7 +7694,17 @@ (define_expand "and<mode>3"
(and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
(match_operand:SWIM 2 "<general_szext_operand>")))]
""
- "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
+{
+ if (<MODE>mode == DImode
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff
+ && REG_P (operands[1]))
+ emit_insn (gen_zero_extendsidi2 (operands[0],
+ gen_lowpart (SImode, operands[1])));
+ else
+ ix86_expand_binary_operator (AND, <MODE>mode, operands);
+ DONE;
+})
(define_insn "*anddi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
Jakub