[SH] PR 49468 - DImode abs

[Oleg Endo <oleg dot endo at t-online dot de>]

Hello,

The attached patch improves the support for DImode absolute value code
on SH.  This is basically the same patch as in the PR, but with added
TARGET_SH1 conditions in the relevant expanders to avoid SH64 failures,
as Kaz pointed out in the PR.
Moreover, it adds a test case and fixes the existing SImode abs test
case to be skipped for SH64, since it is not supported on SH64.

Tested against rev 184589 with 

make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a-single/-mb,
-m4-single/-ml,-m4-single/-mb,
-m4a-single/-ml,-m4a-single/-mb}"

and no new failures.

Cheers,
Oleg

ChangeLog:

2012-03-01  Oleg Endo  <olegendo@gcc.gnu.org>

	PR target/49486
	* config/sh/sh.md (negdi2): Add TARGET_SH1 condition.
	(absdi2): New expander.
	(*absdi2, *negabsdi2, negdi_cond): New insns and splits.


testsuite/ChangeLog:

2012-03-01  Oleg Endo  <olegendo@gcc.gnu.org>

	PR target/49486
	* gcc.target/sh/pr49468-si.c: Skip unsupported test for SH64.
	* gcc.target/sh/pr49468-di.c: New.

Index: gcc/testsuite/gcc.target/sh/pr49468-si.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49468-si.c	(revision 184757)
+++ gcc/testsuite/gcc.target/sh/pr49468-si.c	(working copy)
@@ -1,5 +1,6 @@
 /* Check that 32 bit integer abs is generated as neg instruction and
    conditional branch instead of default branch-free code.  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
 /* { dg-do compile { target "sh*-*-*" } } */
 /* { dg-options "-O1" } */
 /* { dg-final { scan-assembler-times "neg" 2 } } */
Index: gcc/testsuite/gcc.target/sh/pr49468-di.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr49468-di.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr49468-di.c	(revision 0)
@@ -0,0 +1,23 @@
+/* Check that 64 bit integer abs is generated as negc instruction pairs
+   and conditional branch instead of default branch-free code.  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-final { scan-assembler-times "negc" 4 } } */
+
+
+/* Normal integer absolute value.  */
+long long
+abs_0 (long long i)
+{
+  return (i < 0) ? -i : i;
+}
+
+/*  Negated integer absolute value.
+    The generated code should be the same, except that the branch 
+    condition is inverted.  */
+long long
+abs_1 (long long i)
+{
+  return (i > 0) ? -i : i;
+}
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 184757)
+++ gcc/config/sh/sh.md	(working copy)
@@ -4411,7 +4411,7 @@
   [(set (match_operand:DI 0 "arith_reg_dest" "")
 	(neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
    (clobber (reg:SI T_REG))]
-  ""
+  "TARGET_SH1"
   "")
 
 (define_insn_and_split "*negdi2"
@@ -4531,6 +4531,82 @@
   [(set_attr "type" "arith") ;; poor approximation
    (set_attr "length" "4")])
 
+(define_expand "absdi2"
+  [(set (match_operand:DI 0 "arith_reg_dest" "")
+	(abs:DI (match_operand:DI 1 "arith_reg_operand" "")))
+   (clobber (reg:SI T_REG))]
+  "TARGET_SH1"
+  "")
+
+(define_insn_and_split "*absdi2"
+  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+	(abs:DI (match_operand:DI 1 "arith_reg_operand" "r")))]
+  "TARGET_SH1"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+  emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
+  emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
+			     const1_rtx));
+  DONE;
+})
+
+(define_insn_and_split "*negabsdi2"
+  [(set (match_operand:DI 0 "arith_reg_dest" "=r")
+  	(neg:DI (abs:DI (match_operand:DI 1 "arith_reg_operand" "r"))))]
+  "TARGET_SH1"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+
+  emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
+  emit_insn (gen_negdi_cond (operands[0], operands[1], operands[1],
+			     const0_rtx));
+  DONE;
+})
+
+(define_insn_and_split "negdi_cond"
+  [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
+	(if_then_else:DI (eq:SI (reg:SI T_REG)
+				(match_operand:SI 3 "const_int_operand" "M,N"))
+	 (match_operand:DI 1 "arith_reg_operand" "r,r")
+	 (neg:DI (match_operand:DI 2 "arith_reg_operand" "1,1"))))]
+  "TARGET_SH1"
+  "#"
+  "TARGET_SH1"
+  [(const_int 0)]
+{
+  int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
+  int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
+
+  rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
+  rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
+
+  rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
+  rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
+
+  rtx skip_neg_label = gen_label_rtx ();
+
+  emit_insn (gen_movsi (low_dst, low_src));
+  emit_insn (gen_movsi (high_dst, high_src));
+
+  emit_jump_insn (INTVAL (operands[3]) 
+		  ? gen_branch_true (skip_neg_label)
+		  : gen_branch_false (skip_neg_label));
+
+  if (!INTVAL (operands[3]))
+    emit_insn (gen_clrt ());
+
+  emit_insn (gen_negc (low_dst, low_src));
+  emit_label_after (skip_neg_label, emit_insn (gen_negc (high_dst, high_src)));
+  DONE;
+})
 
 ;; -------------------------------------------------------------------------
 ;; Zero extension instructions