Re: debug insns in SMS (was: Re: Debug_insn)

[Revital1 Eres <ERES at il dot ibm dot com>]

Hello Alexandre

> I think this will restore proper functioning to SMS in the presence of
> debug insns.  A while ago, we'd never generate deps of non-debug insns
> on debug insns.  I introduced them to enable sched to adjust (reset)
> debug insns when non-debug insns were moved before them.  I believe it
> is safe to leave them out of the SCCs.  Even though this will end up
> causing some loss of debug info, that's probably unavoidable, and the
> end result after this change is pobably the best we can hope for.  Your
> thoughts?

Thanks for the patch!

I actually discussed this issue with Ayal yesterday.
Ayal also suggested to reconsider the edges that are created in
the DDG between real instructions and debug_insns. Currently, we create
bidirectional anti deps edges between them. This leads to the problem you
were trying to solve in the current patch (described below) where these
extra edges influence the construction of the strongly connected component
and the code generated with and w\o -g. Your patch seems to solve this
problem.
However I can not approve it as I'm not the maintainer (Ayal is).

Another problem with the handling of debug insns in SMS is that
debug_insns instructions are been ignored while scheduling which means
that they do not delimit the scheduling window of the real instructions
they depend on. This could lead to a scenario where the dependencies
between real instruction and debug_insn could be violated as we leave
the debug_insns in their original place after scheduling. I'll try to send
you
an example of this problem as well.

Example of code gen difference when using -g and without it which this
patch tries to solve:
The following nodes are all belong to the same SCC running with -g.
node 1 is not present in this SCC when not using -g.
(the nodes marked in [] are the one that do not
exist with your patch and prevent from node 1 to be added to the SCC
when compiling with -g)

                                                                     node 0
Debug_insn  (ior(MEM(ivtmp.24),MEM(ivtmp.46))
in edges: 1->0, 2->0
out edges: [0->1], [0->4], [0->2]


node 1
Reg 220 = MEM (pre_inc (ivtmp.24))
in edges: [0->1], 1->1
out edges: 1->0, 1->1, 1->3

node 2
Reg 221= MEM (pre_inc (ivtmp.46))
in edges: [0->2], 4->2, 2->2
out edges: 2->0, 2->3, 2->4, 2->2

node 3
Reg 222= ior (220,221)
in edges: 2->3, 1->3
out edges: 3->4

node 4
MEM[pre_inc(196)] = 222
in edges: 3->4, 4->4, [0->4], 2->4
out edges: 4->4, 4->2

Thanks,
Revital