This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [5/9] Main target-independent support for direct interleaving


gcc-patches-owner@gcc.gnu.org wrote on 12/04/2011 04:59:16 PM:

>
> This patch adds vec_load_lanes and vec_store_lanes optabs for
instructions
> like NEON's vldN and vstN.  The optabs are defined this way because the
> vectors must be allocated to a block of consecutive registers.
>
> Tested on x86_64-linux-gnu and arm-linux-gnueabi.  OK to install?

The vectorizer part is fine with me except for:


> @@ -685,9 +761,11 @@ vect_model_store_cost (stmt_vec_info stm
>        first_dr = STMT_VINFO_DATA_REF (stmt_info);
>      }
>
> -  /* Is this an access in a group of stores, which provide strided
access?
> -     If so, add in the cost of the permutes.  */
> -  if (group_size > 1)
> +  /* We assume that the cost of a single store-lanes instruction is
> +     equivalent to the cost of GROUP_SIZE separate stores.  If a strided
> +     access is instead being provided by a load-and-permute operation,

I think it should be 'permute-and-store' and not 'load-and-permute'.

> +     include the cost of the permutes.  */
> +  if (!store_lanes_p && group_size > 1)
>      {
>        /* Uses a high and low interleave operation for each needed
> permute.  */
>        inside_cost = ncopies * exact_log2(group_size) * group_size


Thanks,
Ira


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]