[committed] PR target/38598: extendisi2 for MIPS

[Richard Sandiford <rdsandiford at googlemail dot com>]

This patch fixes PR38598, which is about a missed optimisation.
To quote from the PR:

  mipsisa64-elf-gcc -S -O2 gcc.target/mips/madd-7.c -DNOMIPS16=

  does not produce the expected MADD.  On long64 ABIs like EABI64, the
  loop starts out with an extra extendsidi2 instruction, and although
  this instruction gets removed after reload by a "split to nothing", it
  is still around at register allocation time.

  extendsidi2 does not allow LO operands, so its presence discourages
  the register allocator from using LO for the accumulator.  The fix is
  to add a LO alternative to extendsidi2.

I'd filed this two years ago with the idea of applying it once 4.5 opened,
but I forgot.  Thanks to Andrew for the prod.

Tested on mipsisa64-elf.  Applied.

Richard


gcc/
	PR target/38598
	* config/mips/mips.md (extendsidi2): Add an "l" alternative.
	Update commentary.

gcc/testsuite/
	PR target/38598
	* gcc.target/mips/madd-7.c: Remove -mlong32.
	* gcc.target/mips/msub-7.c: Likewise.

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	2011-03-26 18:30:10.000000000 +0000
+++ gcc/config/mips/mips.md	2011-03-27 10:26:41.000000000 +0100
@@ -2963,20 +2963,26 @@ (define_insn "*zero_extendhi_truncqi"
 ;; Extension insns.
 ;; Those for integer source operand are ordered widest source type first.
 
-;; When TARGET_64BIT, all SImode integer registers should already be in
-;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2).  We can
-;; therefore get rid of register->register instructions if we constrain
-;; the source to be in the same register as the destination.
+;; When TARGET_64BIT, all SImode integer and accumulator registers
+;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
+;; and truncdisi2).  We can therefore get rid of register->register
+;; instructions if we constrain the source to be in the same register as
+;; the destination.
 ;;
-;; The register alternative has type "arith" so that the pre-reload
-;; scheduler will treat it as a move.  This reflects what happens if
-;; the register alternative needs a reload.
+;; Only the pre-reload scheduler sees the type of the register alternatives;
+;; we split them into nothing before the post-reload scheduler runs.
+;; These alternatives therefore have type "move" in order to reflect
+;; what happens if the two pre-reload operands cannot be tied, and are
+;; instead allocated two separate GPRs.  We don't distinguish between
+;; the GPR and LO cases because we don't usually know during pre-reload
+;; scheduling whether an operand will be LO or not.
 (define_insn_and_split "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
+  [(set (match_operand:DI 0 "register_operand" "=d,l,d")
+        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
   "TARGET_64BIT"
   "@
    #
+   #
    lw\t%0,%1"
   "&& reload_completed && register_operand (operands[1], VOIDmode)"
   [(const_int 0)]
@@ -2984,7 +2990,7 @@ (define_insn_and_split "extendsidi2"
   emit_note (NOTE_INSN_DELETED);
   DONE;
 }
-  [(set_attr "move_type" "move,load")
+  [(set_attr "move_type" "move,move,load")
    (set_attr "mode" "DI")])
 
 (define_expand "extend<SHORT:mode><GPR:mode>2"
Index: gcc/testsuite/gcc.target/mips/madd-7.c
===================================================================
--- gcc/testsuite/gcc.target/mips/madd-7.c	2011-03-26 18:30:10.000000000 +0000
+++ gcc/testsuite/gcc.target/mips/madd-7.c	2011-03-27 10:11:25.000000000 +0100
@@ -1,5 +1,4 @@
-/* -mlong32 added because of PR target/38598.  */
-/* { dg-options "-O2 -march=5kc -mlong32" } */
+/* { dg-options "-O2 -march=5kc" } */
 /* { dg-final { scan-assembler-not "\tmul\t" } } */
 /* { dg-final { scan-assembler "\tmadd\t" } } */
 
Index: gcc/testsuite/gcc.target/mips/msub-7.c
===================================================================
--- gcc/testsuite/gcc.target/mips/msub-7.c	2011-03-26 18:30:10.000000000 +0000
+++ gcc/testsuite/gcc.target/mips/msub-7.c	2011-03-27 10:11:25.000000000 +0100
@@ -1,5 +1,4 @@
-/* -mlong32 added because of PR target/38598.  */
-/* { dg-options "-O2 -march=5kc -mlong32" } */
+/* { dg-options "-O2 -march=5kc" } */
 /* { dg-final { scan-assembler-not "\tmul\t" } } */
 /* { dg-final { scan-assembler "\tmsub\t" } } */