This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][i386] Implement ix86_emit_swdivsf more efficiently
- From: Michael Matz <matz at suse dot de>
- To: Richard Guenther <rguenther at suse dot de>
- Cc: gcc-patches at gcc dot gnu dot org, Jan Hubicka <jh at suse dot de>
- Date: Thu, 17 Mar 2011 15:36:24 +0100 (CET)
- Subject: Re: [PATCH][i386] Implement ix86_emit_swdivsf more efficiently
- References: <alpine.LNX.2.00.1103141655270.25982@zhemvz.fhfr.qr>
Hi,
On Mon, 14 Mar 2011, Richard Guenther wrote:
> This rewrites the iteration step of swdivsf to be more register
> efficient (two registers instead of four, no load of a FP constant).
> This matches how ICC emits the rcp sequence and causes no overall loss
> of precision (Micha might still remember the exact details).
I haven't done a full error analysis for the intermediate rounding steps,
but merely a statistical analysis for a subset of dividends and the full
set of divisors. On AMD and Intel processors (that matters because rcpss
accuracy is different on both) the sum of all absolute errors between the
quotient as from divss and the quotients from either our old and the new
method is better for the new method. The max error is 2ulps in each case.
Ciao,
Michael.