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[patch, ARM] PR47246, VFP index range on Thumb-2
- From: Chung-Lin Tang <cltang at codesourcery dot com>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Cc: ramana dot radhakrishnan at arm dot com, Richard Earnshaw <rearnsha at arm dot com>
- Date: Tue, 25 Jan 2011 15:03:07 +0800
- Subject: [patch, ARM] PR47246, VFP index range on Thumb-2
Hi,
This fixes a condition I overlooked in a prior patch. The allowed
Thumb-2 load/store index range for core registers is -256--4096
exclusive, while the coprocessor range is still -1024--1024 like ARM
mode. The valid intersection is then -256--1024.
This actually relates to the problem of having different valid memory
addresses for the same machine mode when load/storing to different
register classes (here SF/DF modes stored in both GPR and FPU regs, with
differing index ranges), which does not seem to be an easy problem
within GCC.
So here's the conservative patch, again tested without regressions. It
corrects other coprocessor cases (FPA, Maverick) together, which should
be correct (not that I've seen Thumb-2 implementations with them)
Okay for trunk?
Thanks,
Chung-Lin