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[PATCH 20/28] mn10300: Emit clr.


From: Richard Henderson <rth@twiddle.net>

---
 gcc/config/mn10300/mn10300.md |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 24c8d11..4f4fdfe 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -70,8 +70,13 @@
 	]
 	(const_int 0))
 )
+
+(define_mode_iterator INT [QI HI SI])
+
 
+;; ----------------------------------------------------------------------
 ;; Pipeline description.
+;; ----------------------------------------------------------------------
 
 ;; The AM33 only has a single pipeline.  It has five stages (fetch,
 ;; decode, execute, memory access, writeback) each of which normally
@@ -480,6 +485,26 @@
 				(const_int 13) (const_int 24))
 		 ])]
 )
+
+;; If the flags register is not live, generate CLR instead of MOV 0.
+;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
+;; but not a win for ADDRESS_REGS.
+(define_peephole2
+  [(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
+  "peep2_regno_dead_p (0, CC_REG)
+   && (REGNO_DATA_P (REGNO (operands[0]), 1)
+       || REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
+  [(parallel [(set (match_dup 0) (const_int 0))
+	      (clobber (reg:CC CC_REG))])]
+)
+
+(define_insn "*mov<mode>_clr"
+  [(set (match_operand:INT 0 "register_operand" "=D")
+	(const_int 0))
+   (clobber (reg:CC CC_REG))]
+  ""
+  "clr %0"
+)
 
 ;; ----------------------------------------------------------------------
 ;; ADD INSTRUCTIONS
-- 
1.7.3.4


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