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[PATCH: PR target/46631] Change operands order so we can use 16bit AND instead of 32bit in thumb2
- From: Carrot Wei <carrot at google dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 30 Nov 2010 15:21:26 -0800
- Subject: [PATCH: PR target/46631] Change operands order so we can use 16bit AND instead of 32bit in thumb2
Hi
An instruction of the following style is 32 bit in thumb2.
and r2, r3, r2
If we change the source operands order, it will be 16 bit.
ands r2, r2, r3
This patch contains a new peephole2 to detect the situation that the all 3
operands of AND are low registers, and the target is the same as the second
source, then replace it with another AND with its source operands exchanged.
This patch passed the regression test on arm qemu.
thanks
Guozhi
ChangeLog:
2010-11-30 Wei Guozhi <carrot@google.com>
PR target/46631
* config/arm/thumb2.md (new peephole2): New peephole2.
2010-11-30 Wei Guozhi <carrot@google.com>
PR target/46631
* gcc.target/arm/pr46631: New testcase.
Index: thumb2.md
===================================================================
--- thumb2.md (revision 167257)
+++ thumb2.md (working copy)
@@ -1118,3 +1118,17 @@
"
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
")
+
+(define_peephole2
+ [(set (match_operand:SI 0 "low_register_operand" "")
+ (and:SI (match_operand:SI 1 "low_register_operand" "")
+ (match_dup 0)))]
+ "TARGET_THUMB2 && peep2_regno_dead_p(0, CC_REGNUM)"
+ [(parallel
+ [(set (match_dup 0)
+ (and:SI (match_dup 0)
+ (match_dup 1)))
+ (clobber (reg:CC CC_REGNUM))])]
+ ""
+)
+
Index: pr46631.c
===================================================================
--- pr46631.c (revision 0)
+++ pr46631.c (revision 0)
@@ -0,0 +1,16 @@
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "ands" } } */
+
+struct S {
+ int bi_buf;
+ int bi_valid;
+};
+
+int tz (struct S* p, int bits, int value)
+{
+ if (p == 0) return 1;
+ p->bi_valid = bits;
+ p->bi_buf = value & ((1 << bits) - 1);
+ return 0;
+}