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Hi, I've just committed the S/390 relevant changes to the 4.6 page. Bye, -Andreas- Index: htdocs/gcc-4.6/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.6/changes.html,v retrieving revision 1.66 retrieving revision 1.68 diff -u -r1.66 -r1.68 --- htdocs/gcc-4.6/changes.html 21 Nov 2010 23:08:45 -0000 1.66 +++ htdocs/gcc-4.6/changes.html 22 Nov 2010 15:00:23 -0000 1.68 @@ -554,6 +554,35 @@ At the moment, Android support is enabled only for ARM.</li> </ul> +<h3>S/390, zSeries and System z9/z10, IBM zEnterprise z196</h3> + <ul> + <li>Support for the zEnterprise z196 processor has been added. + When using the <code>-march=z196</code> option, the compiler + will generate code making use of the following instruction + facilities: + <ul> + <li>Conditional load/store</li> + <li>Distinct-operands</li> + <li>Floating-point-extension</li> + <li>Interlocked-access</li> + <li>Population-count</li> + </ul> + The <code>-mtune=z196</code> option avoids the compare and + branch instructions as well as the load address instruction + with an index register as much as possible and performes + instruction scheduling appropriate for the new out-of-order + pipeline architecture.</li> + <li>When using the <code>-m31 -mzarch</code> options the generated + code still conforms to the 32 bit ABI but uses the general + purpose registers as 64 bit registers internally. This + requires a Linux kernel saving the whole 64 bit registers when + doing a context switch. Kernels providing that feature + indicate that by the 'highgprs' string + in <code>/proc/cpuinfo</code>.</li> + <li>The SSA loop prefetching pass is enabled when + using <code>-O3</code>.</li> + </ul> + <h2>Documentation improvements</h2> <h2>Other significant improvements</h2>
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