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Re: RFA: MN10300: Add redundant comparison elimination pass
- From: Paolo Bonzini <bonzini at gnu dot org>
- To: Nick Clifton <nickc at redhat dot com>
- Cc: rth at redhat dot com, law at redhat dot com, aoliva at redhat dot com, gcc-patches at gcc dot gnu dot org
- Date: Wed, 10 Nov 2010 13:39:54 +0100
- Subject: Re: RFA: MN10300: Add redundant comparison elimination pass
- References: <firstname.lastname@example.org>
On 11/10/2010 09:34 AM, Nick Clifton wrote:
As Richard pointed out my previous patch (for LIW/SETLB) included a
separate feature which should have been submitted on its own. So here
it is - a machine reorg pass to eliminate redundant compares.
The scan could be improved to look further back through the
instruction stream for insns that set the EPSW register, but I am
leaving that for a future patch.
Tested without regressions on an mn10300-elf toolchain.
OK to apply ?
2010-11-10 Nick Clifton<email@example.com>
* config/mn10300/mn10300.c (scan_for_redundant_compares): New
(mn10300_reorg): New function.
--- gcc/config/mn10300/mn10300.c (revision 166474)
+++ gcc/config/mn10300/mn10300.c (working copy)
@@ -2403,6 +2403,128 @@
/* Extract the latency value from the timings attribute. */
return timings< 100 ? (timings % 10) : (timings % 100);
+ rtx cur_insn;
+ /* Look for this sequence:
+ (set (reg X) (arith_op (...)))
+ (set (reg CC) (compare (reg X) (const_int 0)))
+ (set (pc) (if_then_else (EQ|NE (...)) (...) (...)))
+ And remove the compare as the flags in the
+ EPSW register will already be correctly set. */
This pass is only necessary because you are not modeling MODE_CC modes
correctly. You should use a specific mode in SELECT_CC_MODE for EQ/NE
comparisons (e.g. CCZmode) and add patterns like
(set (reg X) (arith_op (...))
(set (reg:CCZ CC) (compare:CCZ (arith_op (...)) (const_int 0)))])
Then combine will be able to change the mode of the COMPARE to CCZmode
(also in the use), and merge the two instructions.
I guess it's okay to do it in mdreorg, but you should at least add a
comment saying that the above would allow a more precise representation
of the instruction stream, and also it would allow better register
allocation in case X dies after the comparison.