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Re: PATCH: Add vzeroupper optimization for AVX
On Tue, Oct 26, 2010 at 9:12 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> Those aren't numbers. They are RTX. I can use enum. Then I need to use
> GEN_INT (xxx). I can do that.
Yes, please use GEN_INT.
>>> +;; Clear the upper 128bits of AVX registers, equivalent to a NOP.
>>> +;; This should be used only when the upper 128bits are unused.
>>> +(define_insn "avx_vzeroupper_nop"
>>> + ?[(unspec_volatile [(match_operand 0 "const_int_operand" "")]
>>> + ? ? ? ? ? ? ? ? UNSPECV_VZEROUPPER_NOP)]
>>> + ?"TARGET_AVX"
>>> + ?"vzeroupper"
>>> + ?[(set_attr "type" "sse")
>>> + ? (set_attr "modrm" "0")
>>> + ? (set_attr "memory" "none")
>>> + ? (set_attr "prefix" "vex")
>>> + ? (set_attr "mode" "OI")])
>>
>> IMO, there is no need for a new insn pattern. UNSPEC_VOLATILEs clobber
>> all regs, pseudos and memory (see sched-deps.c around line 2528), so
>> it looks to me that vzeroupper_nop and existing vzeroupper are no
>> different. Just use the new pattern instead of avx_vzeroupper and
>> *avx_vzeroupper, and iff -mvzeroupper is passed to gcc, then
>> vzeroupper insn is moved around.
>
> I don't think that will work since vzeroupper insns I generated are reall
> nops, by that I mean they don't change register state as far as register
> allocator is concerned. ?The existing vzeroupper pattern clobbers all AVX
> registers, and register allocator will treat all AVX register dead
> after it, which is
> incorrect. For register allocator, my vzeroupper doesn't clobber any registers
> so that register allocator can handle AVX registers properly.
It looks we don't understand each other - using your description
_instead_ of old patterns is what I think should be OK. Some time ago
I have tried to defeat allocator by using AND, SUBREG and ZERO_EXTEND
RTXes, but in any case there was something that didn't work.
Uros.