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Re: [RFC, ARM] Add pipeline description for Cortex-M4 -- try 2


On 09/20/2010 05:23 PM, Paul Brook wrote:
On 09/20/2010 04:59 PM, Paul Brook wrote:
Since there is no Cortex-M4F processor, I updated my patch accordingly.

+;; ALU and multiply is one cycle.
+(define_insn_reservation "cortex_m4_alu" 1

I think it's worth a note here that the default latency assumes no stall and the "bypass" increases the latency.

In my experience it's normal for the default latency to be the maximum
latency.  I don't think this is a problem, just worthy of a comment.

Other than that, ok.

Thanks for review. The last example in


http://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html#Pr
ocessor-pipeline-description

       (define_insn_reservation "float" 3 (eq_attr "type" "float")
                                "f_pipeline, nothing, (port0 | port1))

(define_bypass 4 "float" "simple,mult,div")

shows the former way might also be normal.

Maybe it's just me then. Patch OK.


Committed on trunk. Thanks.


-- Jie Zhang CodeSourcery


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