This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: ARM patch: New cbranchqi, cbranchhi patterns for Thumb-1


On 07/15/2010 04:43 PM, Richard Earnshaw wrote:
> 
> On Thu, 2010-07-15 at 15:24 +0200, Bernd Schmidt wrote:
>> On Thumb-1, comparisons of integer values smaller than a word can be
>> done by shifting the value to the left.  This patch adds a new macroized
>> pattern, cbranch<mode>4_insn, which is used for QImode and HImode, and
>> does exactly that.  Effects:
>>
>> -       lsl     r2, r1, #24
>> -       lsr     r2, r2, #24
>> -       cmp     r2, #0
>> +       lsl     r1, #24
>>         bne     .L195

> This is going to only set the N and Z flags correctly.  V and C will
> have different values.

You're right.  A while ago I posted another patch which introduced
noov_comparison_operator; it seems like that could be used here as well.
 We can handle the other cases by inserting an extra compare with zero.
 New patch attached, this also makes use of the fact that constant
shifts are three-operand even on Thumb-1, so we can use any register as
scratch.

> Also note, the same trick should be usable on ARM and Thumb2 if we don't
> do that already.

On the whole my impression is that being able to manipulate comparison
insns directly makes things a lot easier for the compiler in
TARGET_32BIT mode.  I'm not sure we need this trick, I'd expect the
combiner can already do this.


Bernd

Attachment: cbranchmode2.diff
Description: Text document


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]