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A few weeks ago I changed the cbranchsi4_insn pattern so that it can take advantage of a compare insn output by a previous conditional branch. This patch extends the mechanism to keep track of more kinds of cc-setting insns, in a way similar to that used on cc0 ports. The goal here is to remove the need for special cbranch patterns for essentially every kind of operation. I was trying to modify the andsi pattern for PR42172, and it caused code quality regressions. I'm hoping that this will be less of an issue after this patch. As far as I've observed this patch has little effect on code generation, which is as it should be. We're sometimes able to eliminate a few more comparisons, e.g. for shifts. Discouraging the second alternative of the cbranchsi4_insn pattern tends to make reload work better: - mov r3, #0 - mov r8, r0 mov r5, r7 - cmp r8, r3 + mov r8, r0 + cmp r0, #0 A drawback is the overestimation of insn lengths. Tested with my usual set of ARM multilibs on arm-linux/qemu. Ok? Bernd
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