This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.
Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
---|---|---|
Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |
Other format: | [Raw text] |
Why isn't HImode on operand 1 OK?
My comment in the PR is based on how GCC handles extension of the dividend for 16/32/64 bit operands.
Your suggestion generate a pattern unsupported by hardware before reload
(define_expand "divmod<mode>4" [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") (div:SWIM248 (match_operand:SWIM248 1 "register_operand" "") (match_operand:SWIM248 2 "nonimmediate_operand" ""))) (set (match_operand:SWIM248 3 "register_operand" "") (mod:SWIM248 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "" "")
and introduces an extra register move during split to fix it.
Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
---|---|---|
Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |