This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)


Paul Brook wrote:

>> I'm fairly sure that LDM and STM are uninterruptible instructions on
>> most/all current cores, both ARM's own and those from third parties.  An
>> instruction like "stmia r0, {r0-r15}" will take at least 16 cycles on
>> most processors and interrupts are locked out for the duration.

> It appears the feature I was thinking of[1] was only standardised in ARMv6, 
> and may not be present on earlier cores. It's definitely present on arm11 and 
> cortex-a8/r4/m3 based cores.

OK, so Paul, where does that leave us?  If Phil is right that this is in
fact pretty universal (and not unique to Marvell Feroceon for which this
patch was originally developed, IIRC), do you still object to it going
in?  (I have no opinion the name; if you prefer -mavoid-ldm, that seems
OK, though of course it also applies to STM.)

-- 
Mark Mitchell
CodeSourcery
mark@codesourcery.com
(650) 331-3385 x713


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]