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Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)


On Mon, 2010-05-17 at 12:11 +0100, Paul Brook wrote:
> My understanding is that this option is only useful is only really useful 
> useful on certain third party cores, none of which are supported by FSF gcc. 
> I'd also guess that future (or even present) cores will have a different 
> criteria for generating "low-latency" code.

I'm fairly sure that LDM and STM are uninterruptible instructions on
most/all current cores, both ARM's own and those from third parties.  An
instruction like "stmia r0, {r0-r15}" will take at least 16 cycles on
most processors and interrupts are locked out for the duration.

To take a random-ish example, see the ARM9EJ-S reference manual:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/CHDCBECF.html

So, if you can guarantee that no LDM/STM instructions will be executed,
it does give you a potentially significant improvement in worst-case
interrupt latency.  Obviously this is only true in fairly specialised
software systems but I don't think the issue is restricted to third
party cores.

p.


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