[RFC - ARM] - Fix PR43440 - Fix Neon inline asm register aliasing issues.

[Ramana Radhakrishnan <ramana dot gcc at googlemail dot com>]

Hi,

This is a bug that has come up a couple of times in the past few months 
and is one of the issues with writing inline assembler for Neon as 
described in the audit trail.

This patch has the unhappy side effect of clobbering s0, s1 and s2 
if s3 is used because that's the only way we can indicate that q0 is 
clobbered by the write to s0. Unless we generate the modes for the 
register in the RTL clobber list  or figure out a different way of 
representing this aliasing in the backend both of which I think are 
slightly invasive for stage4, we'll probably have to live with this. If 
anyone can think of a better and less invasive way of doing this, I'm all 
ears.

I've added a testcase for this and will run this through a full 
regression test on arm-eabi for cortex-a8. With some other simple 
testcases that I've tried that exercises quite a bit of the code,
I haven't seen any issues show up.

Comments if any are welcome.

Cheers
Ramana

       * config/arm/arm.c (TARGET_MD_ASM_CLOBBERS): Define.
        (arm_get_clobbers_for_sregs): Likewise.
        (arm_get_clobbers_for_dregs): Likewise.
        (arm_get_clobbers_for_qregs): Likewise.
        (arm_md_asm_clobbers): Likewise.

       * gcc.target/arm/pr43440.c: New testcase.


--
Ramana Radhakrishnan

Attachment: pr43440-patch.txt
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