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Fix ARMv7 VFP ICE
- From: Paul Brook <paul at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 25 Nov 2009 14:00:02 +0000
- Subject: Fix ARMv7 VFP ICE
The patch below fixes an ARM compiler ICE when compiling for ARMv7 and VFP.
On ARM we have two methods of loading large immediates: MOVW/MOVT (aka
HIGH/LOW_SUM) and constant pools. The former are only available for core
registers. Under some circumstances reload gets itself very confused, and ends
up allocating half of the movw/movt sequence to a VFP register, which is then
converted to a constant pool load.
Obviously the the best solution is to not do that, and previous patches have
worked towards this end. However, reload being what it is, there are still
[rare] cases where the failure occurs. Generating sucky code is preferable to
no code at all, so we work around the issue by allowing HIGH in constant
pools.
The original testcase for this is somewhat large and fragile, so there doesn't
seem much point adding it.
Tested on arm-none-eabi.
Applied to SVN trunk.
Paul
2009-11-25 Paul Brook <paul@codesourcery.com>
gcc/
* config/arm/arm.md (consttable_4): Handle (high ...).
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 154647)
+++ gcc/config/arm/arm.md (working copy)
@@ -10957,6 +10957,13 @@ (define_insn "consttable_4"
}
break;
default:
+ /* XXX: Sometimes gcc does something really dumb and ends up with
+ a HIGH in a constant pool entry, usually because it's trying to
+ load into a VFP register. We know this will always be used in
+ combination with a LO_SUM which ignores the high bits, so just
+ strip off the HIGH. */
+ if (GET_CODE (x) == HIGH)
+ x = XEXP (x, 0);
assemble_integer (x, 4, BITS_PER_WORD, 1);
mark_symbol_refs_as_used (x);
break;