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Re: PATCH: Add LWP support for upcoming AMD Orochi processor.
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Harsha Jagasia <harsha dot jagasia at amd dot com>, hubicka at ucw dot cz, rth at redhat dot com, dwarak dot rajagopal at amd dot com, christophe dot harle at amd dot com
- Date: Thu, 1 Oct 2009 09:51:07 +0200
- Subject: Re: PATCH: Add LWP support for upcoming AMD Orochi processor.
Hello!
> This patch is for LWP instruction set support for gcc 4.5 for the
> upcoming AMD Orochi processor. Please see the AMD spec for the LWP
> ISA at http://support.amd.com/us/Processor_TechDocs/43724.pdf
>
> One of the issues I am hoping the maintainers can give guidance on:
>
> - Currently the code for the lwpval and lwpins instructions is
> commented out. These instructions are different from typical
> instructions in that they have no destination register
> (please see the spec). I am not sure how to repesent the patterns
> for the same and would appreciate some input.
Then these instructions should be defined as unspec_volatile. OTOH,
perhaps you should introduce new fixed register to hold LWP state and
change all instructions to correctly depend on this register. Since
LWP state won't be hidden from the compiler, you can define "normal"
insn patterns using "set". This will also benefit scheduler and will
increase general happiness of the compiler ;)
You can just look at FPCR and FPSR handling in i386.md and their
definition in i386.h.
> * config/i386/sse.md (lwp_llwpcbhi1): New lwp pattern.
> ...
There is nothing SSE specific in these patterns, so I think they
should go in i386.md.
Uros.