This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[m32c] add R13 constraint, and disable ivopts.
- From: DJ Delorie <dj at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 24 Sep 2009 16:40:38 -0400
- Subject: [m32c] add R13 constraint, and disable ivopts.
Committed. The ivopts patch "solves" the problem of ivopts not
expecting m32c's size_t != void* configuration.
PR target/41456
* config/m32c/m32c.h (REG_CLASS_CONTENTS): Add R13.
(reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
* config/m32c/m32c.c (m32c_reg_class_from_constraint): Likewise.
* config/m32c/m32c.c (m32c_override_options): Disable -fivopts for
M32C.
Index: config/m32c/m32c.c
===================================================================
--- config/m32c/m32c.c (revision 152143)
+++ config/m32c/m32c.c (working copy)
@@ -419,12 +419,15 @@ m32c_override_options (void)
{
if (target_memregs < 0 || target_memregs > 16)
error ("invalid target memregs value '%d'", target_memregs);
}
else
target_memregs = 16;
+
+ if (TARGET_A24)
+ flag_ivopts = 0;
}
/* Defining data structures for per-function information */
/* The usual; we set up our machine_function data. */
static struct machine_function *
@@ -635,12 +638,14 @@ m32c_reg_class_from_constraint (char c A
if (memcmp (s, "R2w", 3) == 0)
return R2_REGS;
if (memcmp (s, "R3w", 3) == 0)
return R3_REGS;
if (memcmp (s, "R02", 3) == 0)
return R02_REGS;
+ if (memcmp (s, "R13", 3) == 0)
+ return R13_REGS;
if (memcmp (s, "R03", 3) == 0)
return R03_REGS;
if (memcmp (s, "Rdi", 3) == 0)
return DI_REGS;
if (memcmp (s, "Rhl", 3) == 0)
return HL_REGS;
Index: config/m32c/m32c.h
===================================================================
--- config/m32c/m32c.h (revision 152143)
+++ config/m32c/m32c.h (working copy)
@@ -274,12 +274,13 @@ machine_function;
{ 0x000001c0 }, /* CR - sb fb sp */\
{ 0x00000001 }, /* R0 - r0 */\
{ 0x00000004 }, /* R1 - r1 */\
{ 0x00000002 }, /* R2 - r2 */\
{ 0x00000008 }, /* R3 - r3 */\
{ 0x00000003 }, /* R02 - r0r2 */\
+ { 0x0000000c }, /* R13 - r1r3 */\
{ 0x00000005 }, /* HL - r0 r1 */\
{ 0x00000005 }, /* QI - r0 r1 */\
{ 0x0000000a }, /* R23 - r2 r3 */\
{ 0x0000000f }, /* R03 - r0r2 r1r3 */\
{ 0x0000000f }, /* DI - r0r2r1r3 + mems */\
{ 0x00000010 }, /* A0 - a0 */\
@@ -313,12 +314,13 @@ enum reg_class
CR_REGS,
R0_REGS,
R1_REGS,
R2_REGS,
R3_REGS,
R02_REGS,
+ R13_REGS,
HL_REGS,
QI_REGS,
R23_REGS,
R03_REGS,
DI_REGS,
A0_REGS,
@@ -354,12 +356,13 @@ enum reg_class
"CR_REGS", \
"R0_REGS", \
"R1_REGS", \
"R2_REGS", \
"R3_REGS", \
"R02_REGS", \
+"R13_REGS", \
"HL_REGS", \
"QI_REGS", \
"R23_REGS", \
"R03_REGS", \
"DI_REGS", \
"A0_REGS", \