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[PATCH,AVR] Allow zero constraint for general register load
- From: Andrew Hutchinson <andrewhutchinson at cox dot net>
- To: Anatoly Sokolov <aesok at post dot ru>, gcc-patches at gcc dot gnu dot org, "Weddington, Eric" <eweddington at cso dot atmel dot com>
- Date: Sat, 12 Sep 2009 21:11:30 -0400
- Subject: [PATCH,AVR] Allow zero constraint for general register load
This patch removes the unnecessary preference for the narrower "d"
registers when loading zero into a register.
The patch adds zero as an equally preferred source operand as a
register. This contraint is missing for QI and HI mode moves.
It is already present for SI moves and for memory as destination. No
doubt, it was omitted in error.
Tested on avr-gcc C Testsuite with no regressions.
Could you please review and approve?
2009-09-12 Andy Hutchinson <hutchinsonandy@aim.com>
* config/avr.md (movqi): Add zero as equally preferable
constraint as general register.
(movhi): Ditto.
Index: avr.md
===================================================================
--- avr.md (revision 151661)
+++ avr.md (working copy)
@@ -235,7 +235,7 @@
(define_insn "*movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
- (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))]
+ (match_operand:QI 1 "general_operand" "rL,i,rL,Qm,r,q,i"))]
"(register_operand (operands[0],QImode)
|| register_operand (operands[1], QImode) || const0_rtx ==
operands[1])"
"* return output_movqi (insn, operands, NULL);"
@@ -336,7 +336,7 @@
(define_insn "*movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
- (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))]
+ (match_operand:HI 1 "general_operand" "rL,m,rL,i,i,r,q"))]
"(register_operand (operands[0],HImode)
|| register_operand (operands[1],HImode) || const0_rtx == operands[1])"
"* return output_movhi (insn, operands, NULL);"