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[Patch ARM] Fix combinations of compares with shifts.
- From: Ramana Radhakrishnan <ramana dot radhakrishnan at arm dot com>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Cc: rearnsha at arm dot com
- Date: Tue, 11 Aug 2009 14:00:21 +0100
- Subject: [Patch ARM] Fix combinations of compares with shifts.
- Reply-to: ramana dot radhakrishnan at arm dot com
Hi,
This patch enables generation of combinations of compares with shifts
for the attached testcase. We weren't handling SUBREGs in
arm_select_cc_mode for cases where we could generate the compare in a
mode by swapping the operands.
Before this patch for the attached testcase we generated
__mulvsi3:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
smull r0, r1, r1, r0
stmfd sp!, {r3, lr}
mov r3, r0, asr #31
cmp r3, r1
ldmeqfd sp!, {r3, pc}
bl abort
After this patch we generate
__mulvsi3:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
smull r0, r1, r1, r0
stmfd sp!, {r3, lr}
cmp r1, r0, asr #31
ldmeqfd sp!, {r3, pc}
bl abort
Ok to commit after testing on arm-none-eabi cross for Cortex-A8 on
qemu-arm ?
cheers
Ramana
2009-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.target/arm/combine-cmp-shift.c: New test.
2009-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_select_cc_mode): Handle subreg.
--- /dev/null 2009-07-28 14:01:53.286957607 +0100
+++ testsuite/gcc.target/arm/combine-cmp-shift.c 2009-08-11 13:26:48.000000000 +0100
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -mcpu=cortex-a8" } */
+/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+void abort (void);
+
+SItype
+__mulvsi3 (SItype a, SItype b)
+{
+ const DItype w = (DItype) a * (DItype) b;
+ if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1))
+ abort ();
+ return w;
+}
Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c (revision 150624)
+++ config/arm/arm.c (working copy)
@@ -9500,7 +9500,8 @@ arm_select_cc_mode (enum rtx_code op, rt
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
- if (GET_MODE (y) == SImode && GET_CODE (y) == REG
+ if (GET_MODE (y) == SImode
+ && (REG_P (y) || (GET_CODE (y) == SUBREG))
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
|| GET_CODE (x) == ROTATERT))
@@ -9508,7 +9509,8 @@ arm_select_cc_mode (enum rtx_code op, rt
/* This operation is performed swapped, but since we only rely on the Z
flag we don't need an additional mode. */
- if (GET_MODE (y) == SImode && REG_P (y)
+ if (GET_MODE (y) == SImode
+ && (REG_P (y) || (GET_CODE (y) == SUBREG))
&& GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_Zmode;