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Re: Remove SSE5 support
- From: "Jagasia, Harsha" <harsha dot jagasia at amd dot com>
- To: <gcc-patches at gcc dot gnu dot org>, <hubicka at ucw dot cz>, <gerald at pfeifer dot com>, <rth at redhat dot com>, <meissner at linux dot vnet dot ibm dot com>
- Date: Wed, 29 Jul 2009 13:46:51 -0500
- Subject: Re: Remove SSE5 support
Hi Honza, Richard,
>this is patch to remove SSE5 support from compiler.
AMD has publicly announced that the SSE5 instruction set is being
replaced by AVX, FMA4, XOP, CVT16 instruction sets. AMD's upcoming
Orochi processor will support these instruction sets.
We are currently in the process of implementing and testing these
extensions and will be submitting them to the ml. For gcc 4.5, we will
be submitting the FMA4 and XOP changes in phases by stage 1 closure.
For the most part, the changes for the fp fused multiply-add (fma4)
instructions consist of a change in a name of the instructions (i.e. "v"
in front of the corresponding SSE5 instruction names) and a change from
3 operand to 4 operand (i.e the destination register can be distinct
from any of the input registers).
For the most part, the changes for the XOP instructions requires the
removal of those SSE5 instructions that have now become a part of AVX or
SSE4.1 (i.e most of our rounding instructions) and retaining the
remaining with minor changes.
I think it's ok if the maintainers think that it will be cleaner to
remove SSE5 and then have us submit the FMA4 and XOP changes; otherwise
we can submit the FMA4 and XOP patches in phases which will include a
partial removal/replacement of the SSE5 changes also in phases.
Since Dwarak is on vacation, please copy me on any further mails.
Thanks,
Harsha