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[PATCH] Improved trailing bit counting operation


The attached patch improves the __builtin_ctz built-in function, which returns the number of trailing zero bits in a value, by using shorter instruction sequence for ARMv6T2 and later.

Please let me know any comment, or commit it for me since I don't have write access.

Thanks,
	Daniel.

---
07-09-2009  Daniel Gutson  <dgutson@codesourcery.com>

	gcc/
	* config/arm/arm.md (UNSPEC_RBIT): New constant.
	(rbitsi2): New insn.
	(ctzsi2): New expand.

	gcc/testsuite/
	* gcc.target/arm/ctz.c: New test case.


-- Daniel Gutson CodeSourcery www.codesourcery.com
Index: src/gcc-mainline/gcc/testsuite/gcc.target/arm/ctz.c
===================================================================
--- src/gcc-mainline/gcc/testsuite/gcc.target/arm/ctz.c	(revision 0)
+++ src/gcc-mainline/gcc/testsuite/gcc.target/arm/ctz.c	(revision 0)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O2 -march=armv6t2" } */
+
+unsigned int functest(unsigned int x)
+{
+	return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler "rbit" } } */
+/* { dg-final { scan-assembler "ctz" } } */
+/* { dg-final { scan-assembler-not "rsb" } } */
Index: src/gcc-mainline/gcc/config/arm/arm.h
===================================================================
--- src/gcc-mainline/gcc/config/arm/arm.h	(revision 149376)
+++ src/gcc-mainline/gcc/config/arm/arm.h	(working copy)
@@ -2347,6 +2347,7 @@ extern int making_const_table;
 
 /* The arm5 clz instruction returns 32.  */
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  ((VALUE) = 32, 1)
 
 #undef  ASM_APP_OFF
 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
Index: src/gcc-mainline/gcc/config/arm/arm.md
===================================================================
--- src/gcc-mainline/gcc/config/arm/arm.md	(revision 149376)
+++ src/gcc-mainline/gcc/config/arm/arm.md	(working copy)
@@ -100,6 +100,7 @@ (define_constants
    (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a
 			  ; a given symbolic address.
    (UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call.
+   (UNSPEC_RBIT 26)     ; rbit operation.
   ]
 )
 
@@ -10933,6 +10934,26 @@ (define_insn "clzsi2"
   [(set_attr "predicable" "yes")
    (set_attr "insn" "clz")])
 
+(define_insn "rbitsi2"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))]
+  "TARGET_32BIT && arm_arch_thumb2"
+  "rbit%?\\t%0, %1"
+  [(set_attr "predicable" "yes")
+   (set_attr "insn" "clz")])
+
+(define_expand "ctzsi2"
+ [(set (match_operand:SI           0 "s_register_operand" "")
+       (ctz:SI (match_operand:SI  1 "s_register_operand" "")))]
+  "TARGET_32BIT && arm_arch_thumb2"
+  "
+   rtx tmp = gen_reg_rtx (SImode); 
+   emit_insn (gen_rbitsi2 (tmp, operands[1]));
+   emit_insn (gen_clzsi2 (operands[0], tmp));
+   DONE;
+  "
+)
+
 ;; V5E instructions.
 
 (define_insn "prefetch"

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