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Re: [PATCH] MIPS: Fix PR target/39079, __builtin___clear_cache() broken on SMP ISA_HAS_SYNCI systems.
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: David Daney <ddaney at caviumnetworks dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 30 Jun 2009 18:55:54 +0100
- Subject: Re: [PATCH] MIPS: Fix PR target/39079, __builtin___clear_cache() broken on SMP ISA_HAS_SYNCI systems.
- References: <4A49447A.firstname.lastname@example.org>
David Daney <email@example.com> writes:
> From the bug:
> We expand __builtin___clear_cache() to a 'synci' instruction on
> ISA_HAS_SYNCI systems, which invalidates the icache only on the
> local CPU.
> On an SMP system, the caches on all CPUs should be invalidated. To
> achieve this we need to drop back to the old way of doing things by
> using the cache flush system call.
> To fix this, I added a new command line option (-msynci/-mno-synci) that
> enables and disables the generation of the synci instruction for
> clearing the icache. The default is to disable synci, but the default
> can be overridden at configure time with the --with-synci option.
Thanks for doing this. My only real concern is that having an -msynci
option and using it in this way might be confusing. Most other -m
instruction options control whether the ISA supports an instruction,
whereas here we care about whether an available instruction can be
used in a certain way.
What do you think about having an -mmp/-mup pair of options instead?
If the idea's OK, suggestions for better names are welcome.