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Re: PATCH: PR target/40470: unable to find a registe r to spill in class ‘SSE_FIRST_REG’
On Wed, Jun 17, 2009 at 11:18 AM, Vladimir Makarov<firstname.lastname@example.org> wrote:
> I am agree with Jeff and Richard. ?There is one more reason to avoid using
> hard registers. ?Usage of hard registers tends to create more spill failures
> in reload.
It is not like you have a choice here. The register for those insns is fixed.
Sooner or later you have to allocate xmm0 for them.
I will open a bug where gcc generates inefficient code when
hard register isn't used early.
>> I am all for it. Vladimir, how hard to fix RA for this?
> IRA does not generate spill code for insn constraints. ?Reload does it. ?To
> fix it in reload (spill and restore hard registers) is not a trivial task
> and potentially distracting compiler stability for many targets. ?So I'd
> rather avoid it even if it could solve other passes problems like 1st insn
> scheduling for x86/x86_64.
> The originally problem occurs in the combiner (it propagates xmm0 usage
> right after a call through the insn in question). ?So imho I think the best
> way is to fix in the combiner.
I am not sure.