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Re: PowerPC -- single precision FP register constraint


Hi, Michael

This is getting closer.  I successfully bootstrapped on AIX.  The
constraints.md and rs6000.md changes look complete.  There are a few
remaining pieces that need to be cleaned up.

gcc/config/rs6000/dfp.md conversion looks incomplete.  rs6000.md uses
'd' for TFmode, so dfp.md should use 'd' for TDmode.  Also, negdd2_fpr
seems to have been missed and some of the movdd expanders still
mention 'f' constraints.

The ChangeLog should mention the ppu_intrinsics.h changes.

gcc/doc/md.texi section Machine Constraints for PowerPC should be
updated to mention the 'd' constraint and distinguish between 'd' and
'f'.  We need to find the right words to explain the difference
because they are interchangeable for targets that support the full
PowerPC architecture.  Maybe 'd' is a floating point register
containing a double precision value and 'f' is a floating point
register containing a single precision value.

Once I double-check those changes, I think the patch will be ready.

Thanks, David

On Thu, Jun 4, 2009 at 11:31 AM, Michael Eager<eager@eagercon.com> wrote:
> David Edelsohn wrote:
>>
>> On Wed, May 6, 2009 at 8:49 AM, Michael Eager <eager@eagercon.com> wrote:
>>>
>>> The existing FP register constraint 'f' is used for both single-
>>> and double-precision FP values. ?This causes problems with
>>> powerpc-xilinx-eabi, which has only single-precision FP regs.
>>>
>>> The attached patch creates a new register constraint 'd'
>>> for FP registers containing double-precision values.
>>> For a "classic" PowerPC which has double-precision FP regs,
>>> this defaults to FLOAT_REGS, exactly the same as the 'f'
>>> constraint. ?For a PowerPC which only has single-precision
>>> FP regs, this defaults to NO_REGS.
>>>
>>> This passes regression tests with --target=powerpc-eabisim.
>>>
>>> --
>>> Michael Eager ? ?eager@eagercon.com
>>> 1960 Park Blvd., Palo Alto, CA 94306 ?650-325-8077
>>>
>>> 2009-05-06 ?Michael Eager <eager@eagercon.com>
>>>
>>> ? ? ? * config/rs6000/constraints.md: register_constraint "d": New.
>>> ? ? ? * config/rs6000/dfp.md: floatditd2, fixdddi2, fixtddi2: replace 'f'
>>> ? ? ? constraint with 'd'
>>> ? ? ? * config/rs6000/rs6000.md: *fix_truncdfsi2_internal,
>>> ? ? ? fix_truncdfsi2_internal_gfxopt, fix_truncdfsi2_mfpgpr, fctiwz,
>>> stfiwx,
>>> ? ? ? floatdidf2, fix_truncdfdi2, floatdisf2_internal1,
>>> ? ? ? *fix_trunctfsi2_internal, *movdi_internal32, *movdi_mfpgpr,
>>> ? ? ? *movdi_internal64: Same.
>>
>> I am a little confused by your description of the patch versus the
>> patch itself. ?Your patch only changes patterns where floating point
>> registers contain 64 bit integer (double integer) values, not double
>> precision values. ?When the pattern operates on DImode, you sometimes
>> change all occurrences of the "f" constraint and sometimes not --
>> sometimes DDmode and DFmode and sometimes not.
>>
>> For instance, fixdddi2 changes all, fctiwz changes all, but not
>> floatdidf2.
>>
>> What are you really trying to accomplish? ?Is the inconsistency
>> intentional?
>
> The previous patch only changed the constraint to 'd' for double-precision
> FP
> regs where the pattern could have been generated when configured for single-
> precision FP regs. ?In patterns which could only be generated in a double-
> precision FP configuration, the constraint remained 'f'. ?I can appreciate
> your confusion.
>
> The attached patch is more consistent. ?It changes all uses of
> double-precision
> FP register constraints to 'd', only the single-precision FP reg usages have
> the 'f' constraint.
>
>
> --
> Michael Eager ? ?eager@eagercon.com
> 1960 Park Blvd., Palo Alto, CA 94306 ?650-325-8077
>
> 2009-06-04 ?Michael Eager <eager@eagercon.com>
>
> ? ? ? ?* config/rs6000/constraints.md: register_constraint "d": New.
> ? ? ? ?* config/rs6000/dfp.md: extendsddd2, truncddsd2, negdd2_fpr,
> ? ? ? ?*absdd2_fpr, *nabsdd2_fpr, *movdd_hardfloat32,
> ? ? ? ?*movdd_hardfloat64_mfpgpr, *movdd_hardfloat64, *nabstd2_fpr,
> ? ? ? ?extendddtd2, trunctddd2, adddd3, addtd3, subdd3, subtd3, muldd3,
> ? ? ? ?multd3, divdd3, divtd3, *cmpdd_internal1, *cmptd_internal1,
> ? ? ? ?floatditd2, fixdddi2, ftrunctd2, fixtddi2: replace 'f' constraint
> with 'd'
> ? ? ? ?* config/rs6000/ppu_intrinsics.h: __mffs, __mtfsf, __mtfsfi, __fabs,
> ? ? ? ?__fnabs, __fmadd, __fmsub, __fnmadd, __fnmsub, __fsel, __frsqrte,
> ? ? ? ?__fsqrt, __fmul, __fmuls, __frsp, __fcfid, __fctid, __fctidz,
> __fctiw,
> ? ? ? ?__fctiwz: Same.
> ? ? ? ?* config/rs6000/rs6000.md: *extendsfdf2_fpr, *truncdfsf2_fpr,
> ? ? ? ?*fseldfsf4, *negdf2_fpr, *absdf2_fpr, *nabsdf2_fpr, *adddf3_fpr,
> ? ? ? ?*subdf3_fpr, *muldf3_fpr, *divdf3_fpr, recipdf3, fred, sqrtdf2,
> ? ? ? ?*fseldfdf4, *fselsfdf4, *floatsidf2_internal,
> *floatunssidf2_internal,
> ? ? ? ?*fix_truncdfsi2_internal, fix_truncdfsi2_internal_gfxopt,
> fix_truncdfsi2_mfpgpr,
> ? ? ? ?fctiwz, btruncdf2, ceildf2, floordf2, rounddf2, stfiwx, floatdidf2,
> ? ? ? ?fix_truncdfdi2, floatdisf2_internal1, *movdf_hardfloat32,
> ? ? ? ?*movdf_hardfloat64_mfpgpr, *movdf_hardfloat64, *movtf_internal,
> ? ? ? ?*extenddftf2_internal, trunctfdf2_internal1, trunctfdf2_internal2,
> ? ? ? ?trunctfsf2_fprs, fix_trunc_helper, *fix_trunctfsi2_internal,
> ? ? ? ?negtf2_internal, *movdi_internal32, *movdi_mfpgpr, *movdi_internal64,
> ? ? ? ?*movdf_update1, *movdf_update2, *cmpdf_internal1, *cmptf_internal1,
> ? ? ? ?*cmptf_internal2: Same.
>
> diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn
> gcc-orig/gcc/config/rs6000/constraints.md
> gcc/gcc/config/rs6000/constraints.md
> --- gcc-orig/gcc/config/rs6000/constraints.md ? 2009-05-28
> 14:50:32.000000000 -0700
> +++ gcc/gcc/config/rs6000/constraints.md ? ? ? ?2009-05-28
> 14:51:15.000000000 -0700
> @@ -23,6 +23,10 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? FLOAT_REGS : NO_REGS"
> ? "@internal")
>
> +(define_register_constraint "d" "TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? FLOAT_REGS : NO_REGS"
> + ?"@internal")
> +
> ?(define_register_constraint "b" "BASE_REGS"
> ? "@internal")
>
> diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn
> gcc-orig/gcc/config/rs6000/dfp.md gcc/gcc/config/rs6000/dfp.md
> --- gcc-orig/gcc/config/rs6000/dfp.md ? 2009-05-28 14:50:32.000000000 -0700
> +++ gcc/gcc/config/rs6000/dfp.md ? ? ? ?2009-05-28 14:51:15.000000000 -0700
> @@ -128,7 +128,7 @@
> ?;; Hardware support for decimal floating point operations.
>
> ?(define_insn "extendsddd2"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> ? ? ? ?(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
> ? "TARGET_DFP"
> ? "dctdp %0,%1"
> @@ -147,7 +147,7 @@
>
> ?(define_insn "truncddsd2"
> ? [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ? ? ? (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "drsp %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -160,7 +160,7 @@
>
> ?(define_insn "*negdd2_fpr"
> ? [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ? ? ? (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS"
> ? "fneg %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -172,15 +172,15 @@
> ? "")
>
> ?(define_insn "*absdd2_fpr"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS"
> ? "fabs %0,%1"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "*nabsdd2_fpr"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS"
> ? "fnabs %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -281,8 +281,8 @@
> ?;; The "??" is a kludge until we can figure out a more reasonable way
> ?;; of handling these non-offsettable values.
> ?(define_insn "*movdd_hardfloat32"
> - ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=!r,??r,m,f,f,m,!r,!r,!r")
> - ? ? ? (match_operand:DD 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
> + ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=!r,??r,m,d,d,m,!r,!r,!r")
> + ? ? ? (match_operand:DD 1 "input_operand" "r,m,r,d,m,f,G,H,F"))]
> ? "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& (gpc_reg_operand (operands[0], DDmode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DDmode))"
> @@ -417,8 +417,8 @@
> ?; ld/std require word-aligned displacements -> 'Y' constraint.
> ?; List Y->r and r->Y before r->r for reload.
> ?(define_insn "*movdd_hardfloat64_mfpgpr"
> - ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
> - ? ? ? (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
> + ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
> + ? ? ? (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
> ? "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& (gpc_reg_operand (operands[0], DDmode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DDmode))"
> @@ -443,8 +443,8 @@
> ?; ld/std require word-aligned displacements -> 'Y' constraint.
> ?; List Y->r and r->Y before r->r for reload.
> ?(define_insn "*movdd_hardfloat64"
> - ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
> - ? ? ? (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
> + ?[(set (match_operand:DD 0 "nonimmediate_operand"
> "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
> + ? ? ? (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
> ? "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& (gpc_reg_operand (operands[0], DDmode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DDmode))"
> @@ -511,7 +511,7 @@
>
> ?(define_insn "*nabstd2_fpr"
> ? [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
> + ? ? ? (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS"
> ? "fnabs %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -541,7 +541,7 @@
>
> ?(define_insn "extendddtd2"
> ? [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ? ? ? (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dctqpq %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -552,96 +552,96 @@
> ?;; that the result is the first of the pair receiving the result of drdpq.
>
> ?(define_insn "trunctddd2"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_scratch:TD 2 "=f"))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_scratch:TD 2 "=d"))]
> ? "TARGET_DFP"
> ? "drdpq %2,%1\;fmr %0,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "adddd3"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:DD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:DD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dadd %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "addtd3"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:TD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:TD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "daddq %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "subdd3"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:DD (match_operand:DD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dsub %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "subtd3"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:TD (match_operand:TD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dsubq %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "muldd3"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:DD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:DD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dmul %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "multd3"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:TD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:TD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dmulq %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "divdd3"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (div:DD (match_operand:DD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "ddiv %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "divtd3"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (div:TD (match_operand:TD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "ddivq %0,%1,%2"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "*cmpdd_internal1"
> ? [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
> - ? ? ? (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "f")))]
> + ? ? ? (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? (match_operand:DD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dcmpu %0,%1,%2"
> ? [(set_attr "type" "fpcompare")])
>
> ?(define_insn "*cmptd_internal1"
> ? [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
> - ? ? ? (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "f")))]
> + ? ? ? (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? (match_operand:TD 2 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dcmpuq %0,%1,%2"
> ? [(set_attr "type" "fpcompare")])
>
> ?(define_insn "floatditd2"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dcffixq %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -650,8 +650,8 @@
> ?;; This is the first stage of converting it to an integer type.
>
> ?(define_insn "ftruncdd2"
> - ?[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
> - ? ? ? (fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
> + ? ? ? (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "drintn. 0,%0,%1,1"
> ? [(set_attr "type" "fp")])
> @@ -660,8 +660,8 @@
> ?;; This is the second stage of converting decimal float to integer type.
>
> ?(define_insn "fixdddi2"
> - ?[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
> - ? ? ? (fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
> + ? ? ? (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dctfix %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -670,8 +670,8 @@
> ?;; This is the first stage of converting it to an integer type.
>
> ?(define_insn "ftrunctd2"
> - ?[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
> - ? ? ? (fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
> + ? ? ? (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "drintnq. 0,%0,%1,1"
> ? [(set_attr "type" "fp")])
> @@ -680,8 +680,8 @@
> ?;; This is the second stage of converting decimal float to integer type.
>
> ?(define_insn "fixtddi2"
> - ?[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
> - ? ? ? (fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
> + ? ? ? (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
> ? "TARGET_DFP"
> ? "dctfixq %0,%1"
> ? [(set_attr "type" "fp")])
> diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn
> gcc-orig/gcc/config/rs6000/ppu_intrinsics.h
> gcc/gcc/config/rs6000/ppu_intrinsics.h
> --- gcc-orig/gcc/config/rs6000/ppu_intrinsics.h 2009-05-28
> 14:50:32.000000000 -0700
> +++ gcc/gcc/config/rs6000/ppu_intrinsics.h ? ? ?2009-05-28
> 14:51:15.000000000 -0700
> @@ -385,11 +385,11 @@ typedef int __V4SI __attribute__((vector
>
> ?#define __mffs() __extension__ ? ? ? ? ? ? ? ? \
> ? ({double result; ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ?__asm__ volatile ("mffs %0" : "=f" (result)); \
> + ?__asm__ volatile ("mffs %0" : "=d" (result)); \
> ? result; })
>
> ?#define __mtfsf(mask,value) \
> - ?__asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "f" ((double) (value)))
> + ?__asm__ volatile ("mtfsf %0,%1" : : "n" (mask), "d" ((double) (value)))
>
> ?#define __mtfsfi(bits,field) \
> ? __asm__ volatile ("mtfsfi %0,%1" : : "n" (bits), "n" (field))
> @@ -400,8 +400,8 @@ typedef int __V4SI __attribute__((vector
> ?#define __setflm(v) __extension__ ? ? ? ? ? ?\
> ? ({double result; ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? __asm__ volatile ("mffs %0\n\tmtfsf 255,%1" \
> - ? ? ? ? ? ? ? ? ? : "=&f" (result) ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? : "f" ((double) (v))); ? ?\
> + ? ? ? ? ? ? ? ? ? : "=&d" (result) ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? : "d" ((double) (v))); ? ?\
> ? result; })
>
> ?/* __builtin_fabs may perform unnecessary rounding. ?*/
> @@ -416,7 +416,7 @@ static __inline__ double
> ?__fabs(double x)
> ?{
> ? double r;
> - ?__asm__("fabs %0,%1" : "=f"(r) : "f"(x));
> + ?__asm__("fabs %0,%1" : "=d"(r) : "d"(x));
> ? return r;
> ?}
>
> @@ -434,7 +434,7 @@ static __inline__ double
> ?__fnabs(double x)
> ?{
> ? double r;
> - ?__asm__("fnabs %0,%1" : "=f"(r) : "f"(x));
> + ?__asm__("fnabs %0,%1" : "=d"(r) : "d"(x));
> ? return r;
> ?}
>
> @@ -453,7 +453,7 @@ static __inline__ double
> ?__fmadd(double x, double y, double z)
> ?{
> ? double r;
> - ?__asm__("fmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
> + ?__asm__("fmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
> ? return r;
> ?}
>
> @@ -463,7 +463,7 @@ static __inline__ double
> ?__fmsub(double x, double y, double z)
> ?{
> ? double r;
> - ?__asm__("fmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
> + ?__asm__("fmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
> ? return r;
> ?}
>
> @@ -473,7 +473,7 @@ static __inline__ double
> ?__fnmadd(double x, double y, double z)
> ?{
> ? double r;
> - ?__asm__("fnmadd %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
> + ?__asm__("fnmadd %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
> ? return r;
> ?}
>
> @@ -483,7 +483,7 @@ static __inline__ double
> ?__fnmsub(double x, double y, double z)
> ?{
> ? double r;
> - ?__asm__("fnmsub %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
> + ?__asm__("fnmsub %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
> ? return r;
> ?}
>
> @@ -533,7 +533,7 @@ static __inline__ double
> ?__fsel(double x, double y, double z)
> ?{
> ? double r;
> - ?__asm__("fsel %0,%1,%2,%3" : "=f"(r) : "f"(x),"f"(y),"f"(z));
> + ?__asm__("fsel %0,%1,%2,%3" : "=d"(r) : "d"(x),"d"(y),"d"(z));
> ? return r;
> ?}
>
> @@ -552,7 +552,7 @@ static __inline__ double
> ?__frsqrte(double x)
> ?{
> ? double r;
> - ?__asm__("frsqrte %0,%1" : "=f" (r) : "f" (x));
> + ?__asm__("frsqrte %0,%1" : "=d" (r) : "d" (x));
> ? return r;
> ?}
>
> @@ -570,7 +570,7 @@ static __inline__ double
> ?__fsqrt(double x)
> ?{
> ? double r;
> - ?__asm__("fsqrt %0,%1" : "=f"(r) : "f"(x));
> + ?__asm__("fsqrt %0,%1" : "=d"(r) : "d"(x));
> ? return r;
> ?}
>
> @@ -588,7 +588,7 @@ static __inline__ double
> ?__fmul(double a, double b)
> ?{
> ? double d;
> - ?__asm__ ("fmul %0,%1,%2" : "=f" (d) : "f" (a), "f" (b));
> + ?__asm__ ("fmul %0,%1,%2" : "=d" (d) : "d" (a), "d" (b));
> ? return d;
> ?}
>
> @@ -597,7 +597,7 @@ static __inline__ float
> ?__fmuls (float a, float b)
> ?{
> ? float d;
> - ?__asm__ ("fmuls %0,%1,%2" : "=f" (d) : "f" (a), "f" (b));
> + ?__asm__ ("fmuls %0,%1,%2" : "=d" (d) : "f" (a), "f" (b));
> ? return d;
> ?}
>
> @@ -606,7 +606,7 @@ static __inline__ float
> ?__frsp (float a)
> ?{
> ? float d;
> - ?__asm__ ("frsp %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("frsp %0,%1" : "=d" (d) : "f" (a));
> ? return d;
> ?}
>
> @@ -615,7 +615,7 @@ static __inline__ double
> ?__fcfid (long long a)
> ?{
> ? double d;
> - ?__asm__ ("fcfid %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("fcfid %0,%1" : "=d" (d) : "d" (a));
> ? return d;
> ?}
>
> @@ -624,7 +624,7 @@ static __inline__ long long
> ?__fctid (double a)
> ?{
> ? long long d;
> - ?__asm__ ("fctid %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("fctid %0,%1" : "=d" (d) : "d" (a));
> ? return d;
> ?}
>
> @@ -633,7 +633,7 @@ static __inline__ long long
> ?__fctidz (double a)
> ?{
> ? long long d;
> - ?__asm__ ("fctidz %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("fctidz %0,%1" : "=d" (d) : "d" (a));
> ? return d;
> ?}
>
> @@ -642,7 +642,7 @@ static __inline__ int
> ?__fctiw (double a)
> ?{
> ? unsigned long long d;
> - ?__asm__ ("fctiw %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("fctiw %0,%1" : "=d" (d) : "d" (a));
> ? return (int) d;
> ?}
>
> @@ -651,7 +651,7 @@ static __inline__ int
> ?__fctiwz (double a)
> ?{
> ? long long d;
> - ?__asm__ ("fctiwz %0,%1" : "=f" (d) : "f" (a));
> + ?__asm__ ("fctiwz %0,%1" : "=d" (d) : "d" (a));
> ? return (int) d;
> ?}
>
> diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn
> gcc-orig/gcc/config/rs6000/rs6000.md gcc/gcc/config/rs6000/rs6000.md
> --- gcc-orig/gcc/config/rs6000/rs6000.md ? ? ? ?2009-05-28
> 14:50:32.000000000 -0700
> +++ gcc/gcc/config/rs6000/rs6000.md ? ? 2009-05-28 15:29:35.000000000 -0700
> @@ -5119,7 +5119,7 @@
> ? "")
>
> ?(define_insn_and_split "*extendsfdf2_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
> ? ? ? ?(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "@
> @@ -5142,7 +5142,7 @@
>
> ?(define_insn "*truncdfsf2_fpr"
> ? [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
> + ? ? ? (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "frsp %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -5616,7 +5616,7 @@
>
> ?(define_insn "*fseldfsf4"
> ? [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
> - ? ? ? (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
> + ? ? ? (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 4 "zero_fp_constant" "F"))
> ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:SF 2 "gpc_reg_operand" "f")
> ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:SF 3 "gpc_reg_operand" "f")))]
> @@ -5631,8 +5631,8 @@
> ? "")
>
> ?(define_insn "*negdf2_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "fneg %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -5644,15 +5644,15 @@
> ? "")
>
> ?(define_insn "*absdf2_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "fabs %0,%1"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "*nabsdf2_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "fnabs %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -5665,9 +5665,9 @@
> ? "")
>
> ?(define_insn "*adddf3_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "{fa|fadd} %0,%1,%2"
> ? [(set_attr "type" "fp")
> @@ -5681,9 +5681,9 @@
> ? "")
>
> ?(define_insn "*subdf3_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "{fs|fsub} %0,%1,%2"
> ? [(set_attr "type" "fp")
> @@ -5697,9 +5697,9 @@
> ? "")
>
> ?(define_insn "*muldf3_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "{fm|fmul} %0,%1,%2"
> ? [(set_attr "type" "dmul")
> @@ -5715,17 +5715,17 @@
> ? "")
>
> ?(define_insn "*divdf3_fpr"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT &&
> !TARGET_SIMPLE_FPU"
> ? "{fd|fdiv} %0,%1,%2"
> ? [(set_attr "type" "ddiv")])
>
> ?(define_expand "recipdf3"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "f")]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "d")]
> ? ? ? ? ? ? ? ? ? UNSPEC_FRES))]
> ? "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
> ? ?&& flag_finite_math_only && !flag_trapping_math"
> @@ -5735,37 +5735,37 @@
> ?})
>
> ?(define_insn "fred"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")]
> UNSPEC_FRES))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
> UNSPEC_FRES))]
> ? "TARGET_POPCNTB && flag_finite_math_only"
> ? "fre %0,%1"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "f"))
> - ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "d"))
> + ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT"
> ? "{fma|fmadd} %0,%1,%2,%3"
> ? [(set_attr "type" "dmul")
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f"))
> - ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d"))
> + ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT"
> ? "{fms|fmsub} %0,%1,%2,%3"
> ? [(set_attr "type" "dmul")
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand"
> "%f")
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand"
> "f"))
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "f"))))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand"
> "%d")
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand"
> "d"))
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT
> ? ?&& HONOR_SIGNED_ZEROS (DFmode)"
> ? "{fnma|fnmadd} %0,%1,%2,%3"
> @@ -5773,10 +5773,10 @@
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand"
> "f"))
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f"))
> - ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand"
> "d"))
> + ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d"))
> + ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT
> ? ?&& ! HONOR_SIGNED_ZEROS (DFmode)"
> ? "{fnma|fnmadd} %0,%1,%2,%3"
> @@ -5784,10 +5784,10 @@
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand"
> "%f")
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand"
> "f"))
> - ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "f"))))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand"
> "%d")
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand"
> "d"))
> + ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 3 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT
> ? ?&& HONOR_SIGNED_ZEROS (DFmode)"
> ? "{fnms|fnmsub} %0,%1,%2,%3"
> @@ -5795,10 +5795,10 @@
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn ""
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
> - ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f"))))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
> + ? ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d"))))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD &&
> TARGET_DOUBLE_FLOAT
> ? ?&& ! HONOR_SIGNED_ZEROS (DFmode)"
> ? "{fnms|fnmsub} %0,%1,%2,%3"
> @@ -5806,8 +5806,8 @@
> ? ?(set_attr "fp_type" "fp_maddsub_d")])
>
> ?(define_insn "sqrtdf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
> ? "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT"
> ? "fsqrt %0,%1"
> @@ -5865,21 +5865,21 @@
> ?}")
>
> ?(define_insn "*fseldfdf4"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:DF 4 "zero_fp_constant" "F"))
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "f")))]
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "d")))]
> ? "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT"
> ? "fsel %0,%1,%2,%3"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "*fselsfdf4"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> ? ? ? ?(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:SF 4 "zero_fp_constant" "F"))
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "f")))]
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 2 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 3 "gpc_reg_operand" "d")))]
> ? "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
> ? "fsel %0,%1,%2,%3"
> ? [(set_attr "type" "fp")])
> @@ -5935,12 +5935,12 @@
> ?}")
>
> ?(define_insn_and_split "*floatsidf2_internal"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
> ? ? ? ?(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
> ? ?(use (match_operand:SI 2 "gpc_reg_operand" "r"))
> - ? (use (match_operand:DF 3 "gpc_reg_operand" "f"))
> + ? (use (match_operand:DF 3 "gpc_reg_operand" "d"))
> ? ?(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
> - ? (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
> + ? (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
> ? ?(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
> ? "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT"
> ? "#"
> @@ -6003,12 +6003,12 @@
> ?}")
>
> ?(define_insn_and_split "*floatunssidf2_internal"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
> ? ? ? ?(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
> ? ?(use (match_operand:SI 2 "gpc_reg_operand" "r"))
> - ? (use (match_operand:DF 3 "gpc_reg_operand" "f"))
> + ? (use (match_operand:DF 3 "gpc_reg_operand" "d"))
> ? ?(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
> - ? (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
> + ? (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
> ? "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT"
> ? "#"
> ? "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p
> (operands[4]))"
> @@ -6072,8 +6072,8 @@
>
> ?(define_insn_and_split "*fix_truncdfsi2_internal"
> ? [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
> - ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
> + ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
> ? ?(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
> ? "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT"
> @@ -6095,8 +6095,8 @@
>
> ?(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
> ? [(set (match_operand:SI 0 "memory_operand" "=Z")
> - ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
> + ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
> ? "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT
> ? ?&& TARGET_PPC_GFXOPT"
> @@ -6113,8 +6113,8 @@
>
> ?(define_insn_and_split "fix_truncdfsi2_mfpgpr"
> ? [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
> - ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
> + ? ? ? (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
> ? ?(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
> ? "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT"
> @@ -6131,8 +6131,8 @@
> ?; because the first makes it clear that operand 0 is not live
> ?; before the instruction.
> ?(define_insn "fctiwz"
> - ?[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
> + ?[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
> ? ? ? ? ? ? ? ? ? UNSPEC_FCTIWZ))]
> ? "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT"
> @@ -6140,8 +6140,8 @@
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "btruncdf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")]
> UNSPEC_FRIZ))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
> UNSPEC_FRIZ))]
> ? "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "friz %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -6154,8 +6154,8 @@
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "ceildf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")]
> UNSPEC_FRIP))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
> UNSPEC_FRIP))]
> ? "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "frip %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -6168,8 +6168,8 @@
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "floordf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")]
> UNSPEC_FRIM))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
> UNSPEC_FRIM))]
> ? "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "frim %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -6182,8 +6182,8 @@
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "rounddf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")]
> UNSPEC_FRIN))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
> UNSPEC_FRIN))]
> ? "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "frin %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -6198,7 +6198,7 @@
> ?; An UNSPEC is used so we don't have to support SImode in FP registers.
> ?(define_insn "stfiwx"
> ? [(set (match_operand:SI 0 "memory_operand" "=Z")
> - ? ? ? (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
> + ? ? ? (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
> ? ? ? ? ? ? ? ? ? UNSPEC_STFIWX))]
> ? "TARGET_PPC_GFXOPT"
> ? "stfiwx %1,%y0"
> @@ -6211,15 +6211,15 @@
> ? "")
>
> ?(define_insn "floatdidf2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
> ? "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT &&
> TARGET_DOUBLE_FLOAT && TARGET_FPRS"
> ? "fcfid %0,%1"
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "fix_truncdfdi2"
> - ?[(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
> - ? ? ? (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
> + ? ? ? (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
> ? "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT &&
> TARGET_DOUBLE_FLOAT && TARGET_FPRS"
> ? "fctidz %0,%1"
> ? [(set_attr "type" "fp")])
> @@ -6247,8 +6247,8 @@
> ?;; from double rounding.
> ?(define_insn_and_split "floatdisf2_internal1"
> ? [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
> - ? ? ? ?(float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
> - ? (clobber (match_scratch:DF 2 "=f"))]
> + ? ? ? ?(float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
> + ? (clobber (match_scratch:DF 2 "=d"))]
> ? "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_SINGLE_FLOAT"
> ? "#"
> ? "&& reload_completed"
> @@ -8497,8 +8497,8 @@
> ?;; The "??" is a kludge until we can figure out a more reasonable way
> ?;; of handling these non-offsettable values.
> ?(define_insn "*movdf_hardfloat32"
> - ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=!r,??r,m,f,f,m,!r,!r,!r")
> - ? ? ? (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
> + ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=!r,??r,m,d,d,m,!r,!r,!r")
> + ? ? ? (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
> ? "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS &&
> TARGET_DOUBLE_FLOAT
> ? ?&& (gpc_reg_operand (operands[0], DFmode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DFmode))"
> @@ -8637,8 +8637,8 @@
> ?; ld/std require word-aligned displacements -> 'Y' constraint.
> ?; List Y->r and r->Y before r->r for reload.
> ?(define_insn "*movdf_hardfloat64_mfpgpr"
> - ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
> - ? ? ? (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
> + ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
> + ? ? ? (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
> ? "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT
> ? ?&& (gpc_reg_operand (operands[0], DFmode)
> @@ -8664,8 +8664,8 @@
> ?; ld/std require word-aligned displacements -> 'Y' constraint.
> ?; List Y->r and r->Y before r->r for reload.
> ?(define_insn "*movdf_hardfloat64"
> - ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
> - ? ? ? (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
> + ?[(set (match_operand:DF 0 "nonimmediate_operand"
> "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
> + ? ? ? (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
> ? "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& TARGET_DOUBLE_FLOAT
> ? ?&& (gpc_reg_operand (operands[0], DFmode)
> @@ -8715,8 +8715,8 @@
> ?; otherwise reload, given m->f, will try to pick f->f and reload it,
> ?; which doesn't make progress. ?Likewise r->Y must be before r->r.
> ?(define_insn_and_split "*movtf_internal"
> - ?[(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
> - ? ? ? (match_operand:TF 1 "input_operand" ? ? ? ? "f,o,f,YGHF,r,r"))]
> + ?[(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
> + ? ? ? (match_operand:TF 1 "input_operand" ? ? ? ? "d,o,d,YGHF,r,r"))]
> ? "!TARGET_IEEEQUAD
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
> ? ?&& (gpc_reg_operand (operands[0], TFmode)
> @@ -8770,9 +8770,9 @@
> ?})
>
> ?(define_insn_and_split "*extenddftf2_internal"
> - ?[(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
> - ? ? ? (float_extend:TF (match_operand:DF 1 "input_operand"
> "fr,mf,mf,rmGHF")))
> - ? (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
> + ?[(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
> + ? ? ? (float_extend:TF (match_operand:DF 1 "input_operand"
> "dr,md,md,rmGHF")))
> + ? (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
> ? "!TARGET_IEEEQUAD
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
> ? ?&& TARGET_LONG_DOUBLE_128"
> @@ -8813,8 +8813,8 @@
> ? "")
>
> ?(define_insn_and_split "trunctfdf2_internal1"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
> - ? ? ? (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
> + ? ? ? (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
> ? "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
> ? "@
> @@ -8829,8 +8829,8 @@
> ? [(set_attr "type" "fp")])
>
> ?(define_insn "trunctfdf2_internal2"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
> ? "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
> ? ?&& TARGET_LONG_DOUBLE_128"
> @@ -8855,8 +8855,8 @@
>
> ?(define_insn_and_split "trunctfsf2_fprs"
> ? [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
> - ? ? ? (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_scratch:DF 2 "=f"))]
> + ? ? ? (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_scratch:DF 2 "=d"))]
> ? "!TARGET_IEEEQUAD
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
> ? ?&& TARGET_LONG_DOUBLE_128"
> @@ -8885,10 +8885,10 @@
> ?; fadd, but rounding towards zero.
> ?; This is probably not the optimal code sequence.
> ?(define_insn "fix_trunc_helper"
> - ?[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> - ? ? ? (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
> + ?[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> + ? ? ? (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
> ? ? ? ? ? ? ? ? ? UNSPEC_FIX_TRUNC_TF))
> - ? (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
> + ? (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
> ? [(set_attr "type" "fp")
> @@ -8929,10 +8929,10 @@
>
> ?(define_insn_and_split "*fix_trunctfsi2_internal"
> ? [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
> - ? ? ? ?(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
> - ? (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
> - ? (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
> - ? (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
> + ? ? ? ?(fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
> + ? (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
> + ? (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
> + ? (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
> ? ?(clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
> ? "!TARGET_IEEEQUAD
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
> @@ -8962,8 +8962,8 @@
> ? "")
>
> ?(define_insn "negtf2_internal"
> - ?[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
> - ? ? ? (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
> + ?[(set (match_operand:TF 0 "gpc_reg_operand" "=d")
> + ? ? ? (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
> ? "!TARGET_IEEEQUAD
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
> ? "*
> @@ -9028,8 +9028,8 @@
> ?; List r->r after r->"o<>", otherwise reload will try to reload a
> ?; non-offsettable address by using r->r which won't make progress.
> ?(define_insn "*movdi_internal32"
> - ?[(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
> "=o<>,r,r,*f,*f,m,r")
> - ? ? ? (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
> + ?[(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
> "=o<>,r,r,*d,*d,m,r")
> + ? ? ? (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
> ? "! TARGET_POWERPC64
> ? ?&& (gpc_reg_operand (operands[0], DImode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DImode))"
> @@ -9073,8 +9073,8 @@
> ?{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
>
> ?(define_insn "*movdi_mfpgpr"
> - ?[(set (match_operand:DI 0 "nonimmediate_operand"
> "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
> - ? ? ? (match_operand:DI 1 "input_operand"
> "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
> + ?[(set (match_operand:DI 0 "nonimmediate_operand"
> "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
> + ? ? ? (match_operand:DI 1 "input_operand"
> "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
> ? "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
> ? ?&& (gpc_reg_operand (operands[0], DImode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DImode))"
> @@ -9098,8 +9098,8 @@
> ? ?(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
>
> ?(define_insn "*movdi_internal64"
> - ?[(set (match_operand:DI 0 "nonimmediate_operand"
> "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
> - ? ? ? (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
> + ?[(set (match_operand:DI 0 "nonimmediate_operand"
> "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
> + ? ? ? (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
> ? "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT ||
> !TARGET_FPRS)
> ? ?&& (gpc_reg_operand (operands[0], DImode)
> ? ? ? ?|| gpc_reg_operand (operands[1], DImode))"
> @@ -10293,7 +10293,7 @@
> ? [(set_attr "type" "store_ux,store_u")])
>
> ?(define_insn "*movdf_update1"
> - ?[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
> + ?[(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
> ? ? ? ?(mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
> ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
> ? ?(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
> @@ -10309,7 +10309,7 @@
> ?(define_insn "*movdf_update2"
> ? [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
> ? ? ? ? ? ? ? ? ? ? ? ? (match_operand:SI 2 "reg_or_short_operand" "r,I")))
> - ? ? ? (match_operand:DF 3 "gpc_reg_operand" "f,f"))
> + ? ? ? (match_operand:DF 3 "gpc_reg_operand" "d,d"))
> ? ?(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
> ? ? ? ?(plus:SI (match_dup 1) (match_dup 2)))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
> @@ -12186,8 +12186,8 @@
>
> ?(define_insn "*cmpdf_internal1"
> ? [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
> - ? ? ? (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "f")))]
> + ? ? ? (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? (match_operand:DF 2 "gpc_reg_operand" "d")))]
> ? "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
> ? "fcmpu %0,%1,%2"
> ? [(set_attr "type" "fpcompare")])
> @@ -12195,8 +12195,8 @@
> ?;; Only need to compare second words if first words equal
> ?(define_insn "*cmptf_internal1"
> ? [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
> - ? ? ? (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? (match_operand:TF 2 "gpc_reg_operand" "f")))]
> + ? ? ? (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? (match_operand:TF 2 "gpc_reg_operand" "d")))]
> ? "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT &&
> TARGET_LONG_DOUBLE_128"
> ? "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
> @@ -12205,16 +12205,16 @@
>
> ?(define_insn_and_split "*cmptf_internal2"
> ? [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
> - ? ? ? (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
> - ? ? ? ? ? ? ? ? ? ? (match_operand:TF 2 "gpc_reg_operand" "f")))
> - ? ?(clobber (match_scratch:DF 3 "=f"))
> - ? ?(clobber (match_scratch:DF 4 "=f"))
> - ? ?(clobber (match_scratch:DF 5 "=f"))
> - ? ?(clobber (match_scratch:DF 6 "=f"))
> - ? ?(clobber (match_scratch:DF 7 "=f"))
> - ? ?(clobber (match_scratch:DF 8 "=f"))
> - ? ?(clobber (match_scratch:DF 9 "=f"))
> - ? ?(clobber (match_scratch:DF 10 "=f"))]
> + ? ? ? (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
> + ? ? ? ? ? ? ? ? ? ? (match_operand:TF 2 "gpc_reg_operand" "d")))
> + ? ?(clobber (match_scratch:DF 3 "=d"))
> + ? ?(clobber (match_scratch:DF 4 "=d"))
> + ? ?(clobber (match_scratch:DF 5 "=d"))
> + ? ?(clobber (match_scratch:DF 6 "=d"))
> + ? ?(clobber (match_scratch:DF 7 "=d"))
> + ? ?(clobber (match_scratch:DF 8 "=d"))
> + ? ?(clobber (match_scratch:DF 9 "=d"))
> + ? ?(clobber (match_scratch:DF 10 "=d"))]
> ? "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
> ? ?&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT &&
> TARGET_LONG_DOUBLE_128"
> ? "#"
> @@ -14689,7 +14689,7 @@
> ? ? ? ? ? ? ? ? ? ?(use (match_operand:P 1 "symbol_ref_operand" "s"))
> ? ? ? ? ? ? ? ? ? ? (use (match_operand:P 2 "gpc_reg_operand" "r"))
> ? ? ? ? ? ? ? ? ? ?(set (match_operand:DF 3 "memory_operand" "=m")
> - ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 4 "gpc_reg_operand" "f"))])]
> + ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 4 "gpc_reg_operand" "d"))])]
> ? ""
> ? "bl %z1"
> ? [(set_attr "type" "branch")
> @@ -14809,7 +14809,7 @@
> ? ? ? ? ? ? ? ? ? (clobber (match_operand:P 1 "register_operand" "=l"))
> ? ? ? ? ? ? ? ? ? (use (match_operand:P 2 "symbol_ref_operand" "s"))
> ? ? ? ? ? ? ? ? ? ?(use (match_operand:P 3 "gpc_reg_operand" "r"))
> - ? ? ? ? ? ? ? ? ?(set (match_operand:DF 4 "gpc_reg_operand" "=f")
> + ? ? ? ? ? ? ? ? ?(set (match_operand:DF 4 "gpc_reg_operand" "=d")
> ? ? ? ? ? ? ? ? ? ? ? ?(match_operand:DF 5 "memory_operand" "m"))])]
> ?""
> ?"b %z2"
>
>


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