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[Patch POWERPC] Use existing predicates for RTL objects


I'm a beginner within GCC. This patch is according to projects/beginner.html
* Use predicates for RTL objects


It is to use existing predicates for RTL objects at config/rs6000 directory.
Tested on powerpc-eabisim simulator.


Cheers,
Pearly
2009-06-03  Shujing Zhao  <pearly.zhao@oracle.com>

	* config/rs6000/altivec.md: Use REG_P, MEM_P, CONST_INT_P, CALL_P,
	NOTE_P, BARRIER_P and JUMP_TABLE_DATA_P where applicable.
	* config/rs6000/constraints.md: Ditto.
	* config/rs6000/dfp.md: Ditto.
	* config/rs6000/linux64.h: Ditto.
	* config/rs6000/predicates.md: Ditto.
	* config/rs6000/rs6000.c: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/sysv4.h: Ditto.
	* config/rs6000/xcoff.h: Ditto.

Index: config/rs6000/altivec.md
===================================================================
--- config/rs6000/altivec.md	(revision 148116)
+++ config/rs6000/altivec.md	(working copy)
@@ -1875,7 +1875,7 @@ (define_expand "build_vector_mask_for_lo
   rtx addr;
   rtx temp;
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
 
   addr = XEXP (operands[1], 0);
   temp = gen_reg_rtx (GET_MODE (addr));
Index: config/rs6000/constraints.md
===================================================================
--- config/rs6000/constraints.md	(revision 148116)
+++ config/rs6000/constraints.md	(working copy)
@@ -112,7 +112,7 @@ (define_constraint "H"
 (define_memory_constraint "Q"
   "Memory operand that is just an offset from a reg"
   (and (match_code "mem")
-       (match_test "GET_CODE (XEXP (op, 0)) == REG")))
+       (match_test "REG_P (XEXP (op, 0))")))
 
 (define_memory_constraint "Y"
   "Indexed or word-aligned displacement memory operand"
Index: config/rs6000/dfp.md
===================================================================
--- config/rs6000/dfp.md	(revision 148116)
+++ config/rs6000/dfp.md	(working copy)
@@ -40,9 +40,9 @@ (define_split
   [(set (match_operand:SD 0 "gpc_reg_operand" "")
 	(match_operand:SD 1 "const_double_operand" ""))]
   "reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
   "
@@ -195,9 +195,9 @@ (define_split
   [(set (match_operand:DD 0 "gpc_reg_operand" "")
 	(match_operand:DD 1 "const_int_operand" ""))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 1))]
@@ -220,9 +220,9 @@ (define_split
   [(set (match_operand:DD 0 "gpc_reg_operand" "")
 	(match_operand:DD 1 "const_double_operand" ""))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
@@ -245,9 +245,9 @@ (define_split
   [(set (match_operand:DD 0 "gpc_reg_operand" "")
 	(match_operand:DD 1 "const_double_operand" ""))]
   "TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
   "
@@ -302,7 +302,7 @@ (define_insn "*movdd_hardfloat32"
 	return \"mr %0,%1\;mr %L0,%L1\";
     case 1:
       if (rs6000_offsettable_memref_p (operands[1])
-	  || (GET_CODE (operands[1]) == MEM
+	  || (MEM_P (operands[1])
 	      && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
 		  || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
 		  || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
@@ -342,7 +342,7 @@ (define_insn "*movdd_hardfloat32"
 	}
     case 2:
       if (rs6000_offsettable_memref_p (operands[0])
-	  || (GET_CODE (operands[0]) == MEM
+	  || (MEM_P (operands[0])
 	      && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
 		  || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
 		  || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
Index: config/rs6000/linux64.h
===================================================================
--- config/rs6000/linux64.h	(revision 148116)
+++ config/rs6000/linux64.h	(working copy)
@@ -481,7 +481,7 @@ extern int dot_symbols;
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
 	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X) 					\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
        || (GET_CODE (X) == CONST_DOUBLE					\
 	   && ((TARGET_64BIT						\
Index: config/rs6000/predicates.md
===================================================================
--- config/rs6000/predicates.md	(revision 148116)
+++ config/rs6000/predicates.md	(working copy)
@@ -34,7 +34,7 @@ (define_predicate "count_register_operan
 ;; Return 1 if op is an Altivec register.
 (define_predicate "altivec_register_operand"
    (and (match_operand 0 "register_operand")
-	(match_test "GET_CODE (op) != REG
+	(match_test "!REG_P (op)
 		     || ALTIVEC_REGNO_P (REGNO (op))
 		     || REGNO (op) > LAST_VIRTUAL_REGISTER")))
 
@@ -83,7 +83,7 @@ (define_predicate "exact_log2_cint_opera
 ;; Return 1 if op is a register that is not special.
 (define_predicate "gpc_reg_operand"
    (and (match_operand 0 "register_operand")
-	(match_test "(GET_CODE (op) != REG
+	(match_test "(!REG_P (op)
 		      || (REGNO (op) >= ARG_POINTER_REGNUM
 			  && !XER_REGNO_P (REGNO (op)))
 		      || REGNO (op) < MQ_REGNO)
@@ -93,21 +93,21 @@ (define_predicate "gpc_reg_operand"
 ;; Return 1 if op is a register that is a condition register field.
 (define_predicate "cc_reg_operand"
    (and (match_operand 0 "register_operand")
-	(match_test "GET_CODE (op) != REG
+	(match_test "!REG_P (op)
 		     || REGNO (op) > LAST_VIRTUAL_REGISTER
 		     || CR_REGNO_P (REGNO (op))")))
 
 ;; Return 1 if op is a register that is a condition register field not cr0.
 (define_predicate "cc_reg_not_cr0_operand"
    (and (match_operand 0 "register_operand")
-	(match_test "GET_CODE (op) != REG
+	(match_test "!REG_P (op)
 		     || REGNO (op) > LAST_VIRTUAL_REGISTER
 		     || CR_REGNO_NOT_CR0_P (REGNO (op))")))
 
 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
 (define_predicate "cc_reg_not_micro_cr0_operand"
    (and (match_operand 0 "register_operand")
-	(match_test "GET_CODE (op) != REG
+	(match_test "!REG_P (op)
 		     || REGNO (op) > LAST_VIRTUAL_REGISTER
 		     || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
 		     || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
@@ -387,7 +387,7 @@ (define_predicate "word_offset_memref_op
 
   return (GET_CODE (op) != PLUS
 	  || ! REG_P (XEXP (op, 0))
-	  || GET_CODE (XEXP (op, 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (op, 1))
 	  || INTVAL (XEXP (op, 1)) % 4 == 0);
 })
 
@@ -399,7 +399,7 @@ (define_predicate "indexed_or_indirect_o
   if (TARGET_ALTIVEC
       && ALTIVEC_VECTOR_MODE (mode)
       && GET_CODE (op) == AND
-      && GET_CODE (XEXP (op, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (op, 1))
       && INTVAL (XEXP (op, 1)) == -16)
     op = XEXP (op, 0);
 
@@ -444,7 +444,7 @@ (define_predicate "logical_const_operand
 {
   HOST_WIDE_INT opl, oph;
 
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_INT_P (op))
     {
       opl = INTVAL (op) & GET_MODE_MASK (mode);
 
@@ -685,7 +685,7 @@ (define_predicate "lwa_operand"
 	&& (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
 	    || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
 	&& (GET_CODE (XEXP (inner, 0)) != PLUS
-	    || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
+	    || !CONST_INT_P (XEXP (XEXP (inner, 0), 1))
 	    || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
 })
 
@@ -747,7 +747,7 @@ (define_predicate "input_operand"
 
   /* Allow any integer constant.  */
   if (GET_MODE_CLASS (mode) == MODE_INT
-      && (GET_CODE (op) == CONST_INT
+      && (CONST_INT_P (op)
 	  || GET_CODE (op) == CONST_DOUBLE))
     return 1;
 
@@ -859,8 +859,8 @@ (define_predicate "load_multiple_operati
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+      || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -871,14 +871,14 @@ (define_predicate "load_multiple_operati
       rtx elt = XVECEXP (op, 0, i);
 
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != REG
+	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || REGNO (SET_DEST (elt)) != dest_regno + i
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
-	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
 	return 0;
     }
@@ -899,8 +899,8 @@ (define_predicate "store_multiple_operat
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
+      || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -911,14 +911,14 @@ (define_predicate "store_multiple_operat
       rtx elt = XVECEXP (op, 0, i + 1);
 
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != REG
+	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || REGNO (SET_SRC (elt)) != src_regno + i
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
-	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+	  || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
 	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
 	return 0;
     }
@@ -948,9 +948,9 @@ (define_predicate "save_world_operation"
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || ! memory_operand (SET_DEST (elt), DFmode)
-	  || GET_CODE (SET_SRC (elt)) != REG
+	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != DFmode)
 	return 0;
     }
@@ -959,8 +959,8 @@ (define_predicate "save_world_operation"
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != MEM
-	  || GET_CODE (SET_SRC (elt)) != REG
+	  || !MEM_P (SET_DEST (elt))
+	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != V4SImode)
 	return 0;
     }
@@ -969,18 +969,18 @@ (define_predicate "save_world_operation"
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || ! memory_operand (SET_DEST (elt), Pmode)
-	  || GET_CODE (SET_SRC (elt)) != REG
+	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != Pmode)
 	return 0;
     }
 
   elt = XVECEXP (op, 0, index++);
   if (GET_CODE (elt) != SET
-      || GET_CODE (SET_DEST (elt)) != MEM
+      || !MEM_P (SET_DEST (elt))
       || ! memory_operand (SET_DEST (elt), Pmode)
-      || GET_CODE (SET_SRC (elt)) != REG
+      || !REG_P (SET_SRC (elt))
       || REGNO (SET_SRC (elt)) != CR2_REGNO
       || GET_MODE (SET_SRC (elt)) != Pmode)
     return 0;
@@ -1013,9 +1013,9 @@ (define_predicate "restore_world_operati
 
   elt = XVECEXP (op, 0, index++);
   if (GET_CODE (elt) != SET
-      || GET_CODE (SET_SRC (elt)) != MEM
+      || !MEM_P (SET_SRC (elt))
       || ! memory_operand (SET_SRC (elt), Pmode)
-      || GET_CODE (SET_DEST (elt)) != REG
+      || !REG_P (SET_DEST (elt))
       || REGNO (SET_DEST (elt)) != CR2_REGNO
       || GET_MODE (SET_DEST (elt)) != Pmode)
     return 0;
@@ -1024,9 +1024,9 @@ (define_predicate "restore_world_operati
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || ! memory_operand (SET_SRC (elt), Pmode)
-	  || GET_CODE (SET_DEST (elt)) != REG
+	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != Pmode)
 	return 0;
     }
@@ -1035,8 +1035,8 @@ (define_predicate "restore_world_operati
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != MEM
-	  || GET_CODE (SET_DEST (elt)) != REG
+	  || !MEM_P (SET_SRC (elt))
+	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != V4SImode)
 	return 0;
     }
@@ -1045,9 +1045,9 @@ (define_predicate "restore_world_operati
     {
       elt = XVECEXP (op, 0, index++);
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || ! memory_operand (SET_SRC (elt), DFmode)
-	  || GET_CODE (SET_DEST (elt)) != REG
+	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != DFmode)
 	return 0;
     }
@@ -1071,7 +1071,7 @@ (define_predicate "vrsave_operation"
 
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+      || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
       || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
     return 0;
@@ -1117,13 +1117,13 @@ (define_predicate "mfcr_operation"
 
       src_reg = XVECEXP (SET_SRC (exp), 0, 0);
 
-      if (GET_CODE (src_reg) != REG
+      if (!REG_P (src_reg)
 	  || GET_MODE (src_reg) != CCmode
 	  || ! CR_REGNO_P (REGNO (src_reg)))
 	return 0;
 
       if (GET_CODE (exp) != SET
-	  || GET_CODE (SET_DEST (exp)) != REG
+	  || !REG_P (SET_DEST (exp))
 	  || GET_MODE (SET_DEST (exp)) != SImode
 	  || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
 	return 0;
@@ -1134,7 +1134,7 @@ (define_predicate "mfcr_operation"
 	  || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
 	  || XVECLEN (unspec, 0) != 2
 	  || XVECEXP (unspec, 0, 0) != src_reg
-	  || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
+	  || !CONST_INT_P (XVECEXP (unspec, 0, 1))
 	  || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
 	return 0;
     }
@@ -1157,7 +1157,7 @@ (define_predicate "mtcrf_operation"
     return 0;
   src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
 
-  if (GET_CODE (src_reg) != REG
+  if (!REG_P (src_reg)
       || GET_MODE (src_reg) != SImode
       || ! INT_REGNO_P (REGNO (src_reg)))
     return 0;
@@ -1169,7 +1169,7 @@ (define_predicate "mtcrf_operation"
       int maskval;
 
       if (GET_CODE (exp) != SET
-	  || GET_CODE (SET_DEST (exp)) != REG
+	  || !REG_P (SET_DEST (exp))
 	  || GET_MODE (SET_DEST (exp)) != CCmode
 	  || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
 	return 0;
@@ -1180,7 +1180,7 @@ (define_predicate "mtcrf_operation"
 	  || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
 	  || XVECLEN (unspec, 0) != 2
 	  || XVECEXP (unspec, 0, 0) != src_reg
-	  || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
+	  || !CONST_INT_P (XVECEXP (unspec, 0, 1))
 	  || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
 	return 0;
     }
@@ -1201,8 +1201,8 @@ (define_predicate "lmw_operation"
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+      || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -1235,10 +1235,10 @@ (define_predicate "lmw_operation"
       HOST_WIDE_INT newoffset;
 
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_DEST (elt)) != REG
+	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || REGNO (SET_DEST (elt)) != dest_regno + i
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode)
 	return 0;
       newaddr = XEXP (SET_SRC (elt), 0);
@@ -1276,8 +1276,8 @@ (define_predicate "stmw_operation"
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
+      || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -1310,10 +1310,10 @@ (define_predicate "stmw_operation"
       HOST_WIDE_INT newoffset;
 
       if (GET_CODE (elt) != SET
-	  || GET_CODE (SET_SRC (elt)) != REG
+	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || REGNO (SET_SRC (elt)) != src_regno + i
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode)
 	return 0;
       newaddr = XEXP (SET_DEST (elt), 0);
Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c	(revision 148116)
+++ config/rs6000/rs6000.c	(working copy)
@@ -3340,7 +3340,7 @@ build_mask64_2_operands (rtx in, rtx *ou
   unsigned HOST_WIDE_INT c, lsb, m1, m2;
   int shift;
 
-  gcc_assert (GET_CODE (in) == CONST_INT);
+  gcc_assert (CONST_INT_P (in));
 
   c = INTVAL (in);
   if (c & 1)
@@ -3527,7 +3527,7 @@ small_data_operand (rtx op ATTRIBUTE_UNU
   else if (GET_CODE (op) != CONST
 	   || GET_CODE (XEXP (op, 0)) != PLUS
 	   || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
-	   || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
+	   || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
     return 0;
 
   else
@@ -3591,7 +3591,7 @@ legitimate_constant_pool_address_p (rtx 
 {
   return (TARGET_TOC
 	  && GET_CODE (x) == PLUS
-	  && GET_CODE (XEXP (x, 0)) == REG
+	  && REG_P (XEXP (x, 0))
 	  && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
 	  && toc_relative_expr_p (XEXP (x, 1)));
 }
@@ -3615,13 +3615,13 @@ rs6000_legitimate_offset_address_p (enum
 
   if (GET_CODE (x) != PLUS)
     return false;
-  if (GET_CODE (XEXP (x, 0)) != REG)
+  if (!REG_P (XEXP (x, 0)))
     return false;
   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
     return false;
   if (legitimate_constant_pool_address_p (x))
     return true;
-  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+  if (!CONST_INT_P (XEXP (x, 1)))
     return false;
 
   offset = INTVAL (XEXP (x, 1));
@@ -3727,20 +3727,20 @@ avoiding_indexed_address_p (enum machine
 inline bool
 legitimate_indirect_address_p (rtx x, int strict)
 {
-  return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
+  return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
 }
 
 bool
 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
 {
   if (!TARGET_MACHO || !flag_pic
-      || mode != SImode || GET_CODE (x) != MEM)
+      || mode != SImode || !MEM_P (x))
     return false;
   x = XEXP (x, 0);
 
   if (GET_CODE (x) != LO_SUM)
     return false;
-  if (GET_CODE (XEXP (x, 0)) != REG)
+  if (!REG_P (XEXP (x, 0)))
     return false;
   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
     return false;
@@ -3754,7 +3754,7 @@ legitimate_lo_sum_address_p (enum machin
 {
   if (GET_CODE (x) != LO_SUM)
     return false;
-  if (GET_CODE (XEXP (x, 0)) != REG)
+  if (!REG_P (XEXP (x, 0)))
     return false;
   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
     return false;
@@ -3819,8 +3819,8 @@ rs6000_legitimize_address (rtx x, rtx ol
     }
 
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == REG
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && REG_P (XEXP (x, 0))
+      && CONST_INT_P (XEXP (x, 1))
       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
       && !((TARGET_POWERPC64
 	    && (mode == DImode || mode == TImode)
@@ -3840,8 +3840,8 @@ rs6000_legitimize_address (rtx x, rtx ol
       return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
     }
   else if (GET_CODE (x) == PLUS
-	   && GET_CODE (XEXP (x, 0)) == REG
-	   && GET_CODE (XEXP (x, 1)) != CONST_INT
+	   && REG_P (XEXP (x, 0))
+	   && !CONST_INT_P (XEXP (x, 1))
 	   && GET_MODE_NUNITS (mode) == 1
 	   && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
 	       || TARGET_POWERPC64
@@ -3885,8 +3885,8 @@ rs6000_legitimize_address (rtx x, rtx ol
 
          op1 = force_reg (Pmode, op1);
 
-         if (GET_CODE (op2) != REG
-             && (GET_CODE (op2) != CONST_INT
+         if (!REG_P (op2)
+             && (!CONST_INT_P (op2)
                  || !SPE_CONST_OFFSET_OK (INTVAL (op2))
                  || (GET_MODE_SIZE (mode) > 8
                      && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
@@ -3908,7 +3908,7 @@ rs6000_legitimize_address (rtx x, rtx ol
 	   && TARGET_32BIT
 	   && TARGET_NO_TOC
 	   && ! flag_pic
-	   && GET_CODE (x) != CONST_INT
+	   && !CONST_INT_P (x)
 	   && GET_CODE (x) != CONST_DOUBLE
 	   && CONSTANT_P (x)
 	   && GET_MODE_NUNITS (mode) == 1
@@ -3925,7 +3925,7 @@ rs6000_legitimize_address (rtx x, rtx ol
 #if TARGET_MACHO
 	   && ! MACHO_DYNAMIC_NO_PIC_P
 #endif
-	   && GET_CODE (x) != CONST_INT
+	   && !CONST_INT_P (x)
 	   && GET_CODE (x) != CONST_DOUBLE
 	   && CONSTANT_P (x)
 	   && GET_MODE_NUNITS (mode) == 1
@@ -4231,9 +4231,9 @@ rs6000_legitimize_reload_address (rtx x,
   /* We must recognize output that we have already generated ourselves.  */
   if (GET_CODE (x) == PLUS
       && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      && REG_P (XEXP (XEXP (x, 0), 0))
+      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
+      && CONST_INT_P (XEXP (x, 1)))
     {
       push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
 		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
@@ -4264,10 +4264,10 @@ rs6000_legitimize_reload_address (rtx x,
   /* Force ld/std non-word aligned offset into base register by wrapping
      in offset 0.  */
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == REG
+      && REG_P (XEXP (x, 0))
       && REGNO (XEXP (x, 0)) < 32
       && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && (INTVAL (XEXP (x, 1)) & 3) != 0
       && !ALTIVEC_VECTOR_MODE (mode)
       && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
@@ -4282,10 +4282,10 @@ rs6000_legitimize_reload_address (rtx x,
     }
 
   if (GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == REG
+      && REG_P (XEXP (x, 0))
       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
       && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && !SPE_VECTOR_MODE (mode)
       && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
 				  || mode == DDmode || mode == TDmode
@@ -4365,9 +4365,9 @@ rs6000_legitimize_reload_address (rtx x,
       && ALTIVEC_VECTOR_MODE (mode)
       && GET_CODE (x) == AND
       && GET_CODE (XEXP (x, 0)) == PLUS
-      && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
-      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && REG_P (XEXP (XEXP (x, 0), 0))
+      && CONST_INT_P (XEXP (XEXP (x, 0), 1))
+      && CONST_INT_P (XEXP (x, 1))
       && INTVAL (XEXP (x, 1)) == -16)
     {
       x = XEXP (x, 0);
@@ -4412,7 +4412,7 @@ rs6000_legitimate_address_p (enum machin
   if (TARGET_ALTIVEC
       && ALTIVEC_VECTOR_MODE (mode)
       && GET_CODE (x) == AND
-      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && CONST_INT_P (XEXP (x, 1))
       && INTVAL (XEXP (x, 1)) == -16)
     x = XEXP (x, 0);
 
@@ -4438,10 +4438,10 @@ rs6000_legitimate_address_p (enum machin
   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
   if (! reg_ok_strict
       && GET_CODE (x) == PLUS
-      && GET_CODE (XEXP (x, 0)) == REG
+      && REG_P (XEXP (x, 0))
       && (XEXP (x, 0) == virtual_stack_vars_rtx
 	  || XEXP (x, 0) == arg_pointer_rtx)
-      && GET_CODE (XEXP (x, 1)) == CONST_INT)
+      && CONST_INT_P (XEXP (x, 1)))
     return 1;
   if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
     return 1;
@@ -4498,7 +4498,7 @@ rs6000_mode_dependent_address (rtx addr)
   switch (GET_CODE (addr))
     {
     case PLUS:
-      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+      if (CONST_INT_P (XEXP (addr, 1)))
 	{
 	  unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
 	  return val + 12 + 0x8000 >= 0x10000;
@@ -4868,16 +4868,16 @@ rs6000_emit_set_long_const (rtx dest, HO
 static void
 rs6000_eliminate_indexed_memrefs (rtx operands[2])
 {
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) != REG
+  if (MEM_P (operands[0])
+      && !REG_P (XEXP (operands[0], 0))
       && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
       && ! reload_in_progress)
     operands[0]
       = replace_equiv_address (operands[0],
 			       copy_addr_to_reg (XEXP (operands[0], 0)));
 
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) != REG
+  if (MEM_P (operands[1])
+      && !REG_P (XEXP (operands[1], 0))
       && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
       && ! reload_in_progress)
     operands[1]
@@ -4912,8 +4912,8 @@ rs6000_emit_move (rtx dest, rtx source, 
 
   /* Check if GCC is setting up a block move that will end up using FP
      registers as temporaries.  We must make sure this is acceptable.  */
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM
+  if (MEM_P (operands[0])
+      && MEM_P (operands[1])
       && mode == DImode
       && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
 	  || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
@@ -4932,19 +4932,19 @@ rs6000_emit_move (rtx dest, rtx source, 
       return;
     }
 
-  if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
+  if (can_create_pseudo_p () && MEM_P (operands[0])
       && !gpc_reg_operand (operands[1], mode))
     operands[1] = force_reg (mode, operands[1]);
 
   if (mode == SFmode && ! TARGET_POWERPC
       && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
-      && GET_CODE (operands[0]) == MEM)
+      && MEM_P (operands[0]))
     {
       int regnum;
 
       if (reload_in_progress || reload_completed)
 	regnum = true_regnum (operands[1]);
-      else if (GET_CODE (operands[1]) == REG)
+      else if (REG_P (operands[1]))
 	regnum = REGNO (operands[1]);
       else
 	regnum = -1;
@@ -5071,7 +5071,7 @@ rs6000_emit_move (rtx dest, rtx source, 
     case HImode:
     case QImode:
       if (CONSTANT_P (operands[1])
-	  && GET_CODE (operands[1]) != CONST_INT)
+	  && !CONST_INT_P (operands[1]))
 	operands[1] = force_const_mem (mode, operands[1]);
       break;
 
@@ -5130,7 +5130,7 @@ rs6000_emit_move (rtx dest, rtx source, 
 	  && mode == Pmode
 	  && CONSTANT_P (operands[1])
 	  && GET_CODE (operands[1]) != HIGH
-	  && GET_CODE (operands[1]) != CONST_INT)
+	  && !CONST_INT_P (operands[1]))
 	{
 	  rtx target = (!can_create_pseudo_p ()
 			? operands[0]
@@ -5192,11 +5192,11 @@ rs6000_emit_move (rtx dest, rtx source, 
 	}
       else if (mode == Pmode
 	       && CONSTANT_P (operands[1])
-	       && ((GET_CODE (operands[1]) != CONST_INT
+	       && ((!CONST_INT_P (operands[1])
 		    && ! easy_fp_constant (operands[1], mode))
-		   || (GET_CODE (operands[1]) == CONST_INT
+		   || (CONST_INT_P (operands[1])
 		       && num_insns_constant (operands[1], mode) > 2)
-		   || (GET_CODE (operands[0]) == REG
+		   || (REG_P (operands[0])
 		       && FP_REGNO_P (REGNO (operands[0]))))
 	       && GET_CODE (operands[1]) != HIGH
 	       && ! legitimate_constant_pool_address_p (operands[1])
@@ -5287,7 +5287,7 @@ rs6000_emit_move (rtx dest, rtx source, 
   /* Above, we may have called force_const_mem which may have returned
      an invalid address.  If we can, fix this up; otherwise, reload will
      have to deal with it.  */
-  if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
+  if (MEM_P (operands[1]) && ! reload_in_progress)
     operands[1] = validize_mem (operands[1]);
 
  emit_set:
@@ -6719,13 +6719,13 @@ setup_incoming_varargs (CUMULATIVE_ARGS 
 	    {
 	      rtx reg_save_area
 		= assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
-	      gcc_assert (GET_CODE (reg_save_area) == MEM);
+	      gcc_assert (MEM_P (reg_save_area));
 	      reg_save_area = XEXP (reg_save_area, 0);
 	      if (GET_CODE (reg_save_area) == PLUS)
 		{
 		  gcc_assert (XEXP (reg_save_area, 0)
 			      == virtual_stack_vars_rtx);
-		  gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
+		  gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
 		  offset += INTVAL (XEXP (reg_save_area, 1));
 		}
 	      else
@@ -7856,7 +7856,7 @@ rs6000_expand_unop_builtin (enum insn_co
       || icode == CODE_FOR_spe_evsplati)
     {
       /* Only allow 5-bit *signed* literals.  */
-      if (GET_CODE (op0) != CONST_INT
+      if (!CONST_INT_P (op0)
 	  || INTVAL (op0) > 15
 	  || INTVAL (op0) < -16)
 	{
@@ -10827,7 +10827,7 @@ expand_block_clear (rtx operands[])
   rtx orig_dest = operands[0];
   rtx bytes_rtx	= operands[1];
   rtx align_rtx = operands[3];
-  bool constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  bool constp	= (CONST_INT_P (bytes_rtx));
   HOST_WIDE_INT align;
   HOST_WIDE_INT bytes;
   int offset;
@@ -10839,7 +10839,7 @@ expand_block_clear (rtx operands[])
     return 0;
 
   /* This must be a fixed size alignment  */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
   align = INTVAL (align_rtx) * BITS_PER_UNIT;
 
   /* Anything to clear? */
@@ -10930,7 +10930,7 @@ expand_block_move (rtx operands[])
   rtx orig_src	= operands[1];
   rtx bytes_rtx	= operands[2];
   rtx align_rtx = operands[3];
-  int constp	= (GET_CODE (bytes_rtx) == CONST_INT);
+  int constp	= (CONST_INT_P (bytes_rtx));
   int align;
   int bytes;
   int offset;
@@ -10943,7 +10943,7 @@ expand_block_move (rtx operands[])
     return 0;
 
   /* This must be a fixed size alignment */
-  gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+  gcc_assert (CONST_INT_P (align_rtx));
   align = INTVAL (align_rtx) * BITS_PER_UNIT;
 
   /* Anything to move? */
@@ -11228,7 +11228,7 @@ includes_rshift_p (rtx shiftop, rtx ando
 int
 includes_rldic_lshift_p (rtx shiftop, rtx andop)
 {
-  if (GET_CODE (andop) == CONST_INT)
+  if (CONST_INT_P (andop))
     {
       HOST_WIDE_INT c, lsb, shift_mask;
 
@@ -11321,7 +11321,7 @@ includes_rldic_lshift_p (rtx shiftop, rt
 int
 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
 {
-  if (GET_CODE (andop) == CONST_INT)
+  if (CONST_INT_P (andop))
     {
       HOST_WIDE_INT c, lsb, shift_mask;
 
@@ -11411,7 +11411,7 @@ int
 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
 {
   /* We might have been passed a SUBREG.  */
-  if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
+  if (!REG_P (reg1) || !REG_P (reg2))
     return 0;
 
   /* We might have been passed non floating point registers.  */
@@ -11444,18 +11444,18 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem
   if (GET_CODE (addr1) == PLUS)
     {
       /* If not a REG, return zero.  */
-      if (GET_CODE (XEXP (addr1, 0)) != REG)
+      if (!REG_P (XEXP (addr1, 0)))
 	return 0;
       else
 	{
 	  reg1 = REGNO (XEXP (addr1, 0));
 	  /* The offset must be constant!  */
-	  if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
+	  if (!CONST_INT_P (XEXP (addr1, 1)))
 	    return 0;
 	  offset1 = INTVAL (XEXP (addr1, 1));
 	}
     }
-  else if (GET_CODE (addr1) != REG)
+  else if (!REG_P (addr1))
     return 0;
   else
     {
@@ -11468,18 +11468,18 @@ mems_ok_for_quad_peep (rtx mem1, rtx mem
   if (GET_CODE (addr2) == PLUS)
     {
       /* If not a REG, return zero.  */
-      if (GET_CODE (XEXP (addr2, 0)) != REG)
+      if (!REG_P (XEXP (addr2, 0)))
 	return 0;
       else
 	{
 	  reg2 = REGNO (XEXP (addr2, 0));
 	  /* The offset must be constant. */
-	  if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
+	  if (!CONST_INT_P (XEXP (addr2, 1)))
 	    return 0;
 	  offset2 = INTVAL (XEXP (addr2, 1));
 	}
     }
-  else if (GET_CODE (addr2) != REG)
+  else if (!REG_P (addr2))
     return 0;
   else
     {
@@ -11637,7 +11637,7 @@ rs6000_secondary_reload_class (enum reg_
 	return BASE_REGS;
     }
 
-  if (GET_CODE (in) == REG)
+  if (REG_P (in))
     {
       regno = REGNO (in);
       if (regno >= FIRST_PSEUDO_REGISTER)
@@ -11703,7 +11703,7 @@ ccr_bit (rtx op, int scc_p)
 
   reg = XEXP (op, 0);
 
-  gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
+  gcc_assert (REG_P (reg) && CR_REGNO_P (REGNO (reg)));
 
   cc_mode = GET_MODE (reg);
   cc_regnum = REGNO (reg);
@@ -11773,11 +11773,11 @@ rs6000_init_machine_status (void)
 
 /* These macros test for integers and extract the low-order bits.  */
 #define INT_P(X)  \
-((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)	\
+((CONST_INT_P (X) || GET_CODE (X) == CONST_DOUBLE)	\
  && GET_MODE (X) == VOIDmode)
 
 #define INT_LOWPART(X) \
-  (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
+  (CONST_INT_P (X) ? INTVAL (X) : CONST_DOUBLE_LOW (X))
 
 int
 extract_MB (rtx op)
@@ -11946,7 +11946,7 @@ print_operand (FILE *file, rtx x, int co
 	 write 'l'.  Otherwise, write 'r'.  This is a kludge to fix a bug
 	 in the AIX assembler where "sri" with a zero shift count
 	 writes a trash instruction.  */
-      if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
+      if (CONST_INT_P (x) && (INTVAL (x) & 31) == 0)
 	putc ('l', file);
       else
 	putc ('r', file);
@@ -11972,7 +11972,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'c':
       /* X is a CR register.  Print the number of the GT bit of the CR.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
+      if (!REG_P (x) || ! CR_REGNO_P (REGNO (x)))
 	output_operand_lossage ("invalid %%E value");
       else
 	fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
@@ -11980,7 +11980,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'D':
       /* Like 'J' but get to the GT bit only.  */
-      gcc_assert (GET_CODE (x) == REG);
+      gcc_assert (REG_P (x));
 
       /* Bit 1 is GT bit.  */
       i = 4 * (REGNO (x) - CR0_REGNO) + 1;
@@ -11991,7 +11991,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'E':
       /* X is a CR register.  Print the number of the EQ bit of the CR */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
+      if (!REG_P (x) || ! CR_REGNO_P (REGNO (x)))
 	output_operand_lossage ("invalid %%E value");
       else
 	fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
@@ -12000,7 +12000,7 @@ print_operand (FILE *file, rtx x, int co
     case 'f':
       /* X is a CR register.  Print the shift count needed to move it
 	 to the high-order four bits.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
+      if (!REG_P (x) || ! CR_REGNO_P (REGNO (x)))
 	output_operand_lossage ("invalid %%f value");
       else
 	fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
@@ -12009,7 +12009,7 @@ print_operand (FILE *file, rtx x, int co
     case 'F':
       /* Similar, but print the count for the rotate in the opposite
 	 direction.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
+      if (!REG_P (x) || ! CR_REGNO_P (REGNO (x)))
 	output_operand_lossage ("invalid %%F value");
       else
 	fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
@@ -12018,7 +12018,7 @@ print_operand (FILE *file, rtx x, int co
     case 'G':
       /* X is a constant integer.  If it is negative, print "m",
 	 otherwise print "z".  This is to make an aze or ame insn.  */
-      if (GET_CODE (x) != CONST_INT)
+      if (!CONST_INT_P (x))
 	output_operand_lossage ("invalid %%G value");
       else if (INTVAL (x) >= 0)
 	putc ('z', file);
@@ -12093,7 +12093,7 @@ print_operand (FILE *file, rtx x, int co
 	  if (GET_CODE (XEXP (x, 0)) != PLUS
 	      || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
 		  && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
-	      || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
+	      || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
 	    output_operand_lossage ("invalid %%K value");
 	  print_operand_address (file, XEXP (XEXP (x, 0), 0));
 	  fputs ("@l", file);
@@ -12111,9 +12111,9 @@ print_operand (FILE *file, rtx x, int co
     case 'L':
       /* Write second word of DImode or DFmode reference.  Works on register
 	 or non-indexed memory only.  */
-      if (GET_CODE (x) == REG)
+      if (REG_P (x))
 	fputs (reg_names[REGNO (x) + 1], file);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  /* Handle possible auto-increment.  Since it is pre-increment and
 	     we have already done it, we can just use an offset of word.  */
@@ -12182,7 +12182,7 @@ print_operand (FILE *file, rtx x, int co
     case 'P':
       /* The operand must be an indirect memory reference.  The result
 	 is the register name.  */
-      if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
+      if (!MEM_P (x) || !REG_P (XEXP (x, 0))
 	  || REGNO (XEXP (x, 0)) >= 32)
 	output_operand_lossage ("invalid %%P value");
       else
@@ -12236,7 +12236,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'R':
       /* X is a CR register.  Print the mask for `mtcrf'.  */
-      if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
+      if (!REG_P (x) || ! CR_REGNO_P (REGNO (x)))
 	output_operand_lossage ("invalid %%R value");
       else
 	fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
@@ -12282,7 +12282,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 't':
       /* Like 'J' but get to the OVERFLOW/UNORDERED bit.  */
-      gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
+      gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
 
       /* Bit 3 is OV bit.  */
       i = 4 * (REGNO (x) - CR0_REGNO) + 3;
@@ -12293,7 +12293,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'T':
       /* Print the symbolic name of a branch target register.  */
-      if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
+      if (!REG_P (x) || (REGNO (x) != LR_REGNO
 				  && REGNO (x) != CTR_REGNO))
 	output_operand_lossage ("invalid %%T value");
       else if (REGNO (x) == LR_REGNO)
@@ -12322,7 +12322,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'U':
       /* Print `u' if this has an auto-increment or auto-decrement.  */
-      if (GET_CODE (x) == MEM
+      if (MEM_P (x)
 	  && (GET_CODE (XEXP (x, 0)) == PRE_INC
 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC
 	      || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
@@ -12380,7 +12380,7 @@ print_operand (FILE *file, rtx x, int co
 
     case 'W':
       /* MB value for a PowerPC64 rldic operand.  */
-      val = (GET_CODE (x) == CONST_INT
+      val = (CONST_INT_P (x)
 	     ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
 
       if (val < 0)
@@ -12391,7 +12391,7 @@ print_operand (FILE *file, rtx x, int co
 	    break;
 
 #if HOST_BITS_PER_WIDE_INT == 32
-      if (GET_CODE (x) == CONST_INT && i >= 0)
+      if (CONST_INT_P (x) && i >= 0)
 	i += 32;  /* zero-extend high-part was all 0's */
       else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
 	{
@@ -12411,7 +12411,7 @@ print_operand (FILE *file, rtx x, int co
       return;
 
     case 'X':
-      if (GET_CODE (x) == MEM
+      if (MEM_P (x)
 	  && (legitimate_indexed_address_p (XEXP (x, 0), 0)
 	      || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
 		  && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
@@ -12420,9 +12420,9 @@ print_operand (FILE *file, rtx x, int co
 
     case 'Y':
       /* Like 'L', for third word of TImode  */
-      if (GET_CODE (x) == REG)
+      if (REG_P (x))
 	fputs (reg_names[REGNO (x) + 2], file);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
@@ -12469,9 +12469,9 @@ print_operand (FILE *file, rtx x, int co
 
     case 'Z':
       /* Like 'L', for last word of TImode.  */
-      if (GET_CODE (x) == REG)
+      if (REG_P (x))
 	fputs (reg_names[REGNO (x) + 3], file);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
 	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
@@ -12491,7 +12491,7 @@ print_operand (FILE *file, rtx x, int co
       {
 	rtx tmp;
 
-	gcc_assert (GET_CODE (x) == MEM);
+	gcc_assert (MEM_P (x));
 
 	tmp = XEXP (x, 0);
 
@@ -12502,18 +12502,18 @@ print_operand (FILE *file, rtx x, int co
 		|| GET_MODE (x) == TImode))
 	  {
 	    /* Handle [reg].  */
-	    if (GET_CODE (tmp) == REG)
+	    if (REG_P (tmp))
 	      {
 		fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
 		break;
 	      }
 	    /* Handle [reg+UIMM].  */
 	    else if (GET_CODE (tmp) == PLUS &&
-		     GET_CODE (XEXP (tmp, 1)) == CONST_INT)
+		     CONST_INT_P (XEXP (tmp, 1)))
 	      {
 		int x;
 
-		gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
+		gcc_assert (REG_P (XEXP (tmp, 0)));
 
 		x = INTVAL (XEXP (tmp, 1));
 		fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
@@ -12524,10 +12524,10 @@ print_operand (FILE *file, rtx x, int co
 	  }
 	if (TARGET_ALTIVEC
 	    && GET_CODE (tmp) == AND
-	    && GET_CODE (XEXP (tmp, 1)) == CONST_INT
+	    && CONST_INT_P (XEXP (tmp, 1))
 	    && INTVAL (XEXP (tmp, 1)) == -16)
 	  tmp = XEXP (tmp, 0);
-	if (GET_CODE (tmp) == REG)
+	if (REG_P (tmp))
 	  fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
 	else
 	  {
@@ -12550,9 +12550,9 @@ print_operand (FILE *file, rtx x, int co
       }
 
     case 0:
-      if (GET_CODE (x) == REG)
+      if (REG_P (x))
 	fprintf (file, "%s", reg_names[REGNO (x)]);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  /* We need to handle PRE_INC and PRE_DEC here, since we need to
 	     know the width from the mode.  */
@@ -12585,7 +12585,7 @@ print_operand (FILE *file, rtx x, int co
 void
 print_operand_address (FILE *file, rtx x)
 {
-  if (GET_CODE (x) == REG)
+  if (REG_P (x))
     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
   else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
 	   || GET_CODE (x) == LABEL_REF)
@@ -12597,7 +12597,7 @@ print_operand_address (FILE *file, rtx x
       else
 	gcc_assert (!TARGET_TOC);
     }
-  else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
+  else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 1)))
     {
       gcc_assert (REG_P (XEXP (x, 0)));
       if (REGNO (XEXP (x, 0)) == 0)
@@ -12607,11 +12607,11 @@ print_operand_address (FILE *file, rtx x
 	fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
 		 reg_names[ REGNO (XEXP (x, 1)) ]);
     }
-  else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+  else if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
     fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
 	     INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
 #if TARGET_ELF
-  else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
+  else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
 	   && CONSTANT_P (XEXP (x, 1)))
     {
       output_addr_const (file, XEXP (x, 1));
@@ -12619,7 +12619,7 @@ print_operand_address (FILE *file, rtx x
     }
 #endif
 #if TARGET_MACHO
-  else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
+  else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
 	   && CONSTANT_P (XEXP (x, 1)))
     {
       fprintf (file, "lo16(");
@@ -12689,7 +12689,7 @@ rs6000_assemble_integer (rtx x, unsigned
 	  && in_section != text_section
 	  && !unlikely_text_section_p (in_section)
 	  && !recurse
-	  && GET_CODE (x) != CONST_INT
+	  && !CONST_INT_P (x)
 	  && GET_CODE (x) != CONST_DOUBLE
 	  && CONSTANT_P (x))
 	{
@@ -13263,8 +13263,8 @@ output_e500_flip_gt_bit (rtx dst, rtx sr
   static char string[64];
   int a, b;
 
-  gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
-	      && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
+  gcc_assert (REG_P (dst) && CR_REGNO_P (REGNO (dst))
+	      && REG_P (src) && CR_REGNO_P (REGNO (src)));
 
   /* GT bit.  */
   a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
@@ -14327,7 +14327,7 @@ rs6000_split_multireg_move (rtx dst, rtx
 	    j = REGNO (breg) - REGNO (dst);
 	}
 
-      if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
+      if (MEM_P (dst) && INT_REGNO_P (reg))
 	{
 	  rtx breg;
 
@@ -14523,7 +14523,7 @@ compute_save_world_info (rs6000_stack_t 
     {
       rtx insn;
       for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
-	if ( GET_CODE (insn) == CALL_INSN
+	if ( CALL_P (insn)
 	     && SIBLING_CALL_P (insn))
 	  {
 	    info_ptr->world_save_p = 0;
@@ -15217,9 +15217,7 @@ rs6000_invalid_within_doloop (const_rtx 
   if (CALL_P (insn))
     return "Function call in the loop.";
 
-  if (JUMP_P (insn)
-      && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
-	  || GET_CODE (PATTERN (insn)) == ADDR_VEC))
+  if (JUMP_TABLE_DATA_P (insn))
     return "Computed branch in the loop.";
 
   return NULL;
@@ -15649,7 +15647,7 @@ rs6000_frame_related (rtx insn, rtx reg,
       temp = simplify_rtx (SET_DEST (set));
       if (temp)
 	SET_DEST (set) = temp;
-      if (GET_CODE (SET_DEST (set)) == MEM)
+      if (MEM_P (SET_DEST (set)))
 	{
 	  temp = simplify_rtx (XEXP (SET_DEST (set), 0));
 	  if (temp)
@@ -15672,7 +15670,7 @@ rs6000_frame_related (rtx insn, rtx reg,
 	    temp = simplify_rtx (SET_DEST (set));
 	    if (temp)
 	      SET_DEST (set) = temp;
-	    if (GET_CODE (SET_DEST (set)) == MEM)
+	    if (MEM_P (SET_DEST (set)))
 	      {
 		temp = simplify_rtx (XEXP (SET_DEST (set), 0));
 		if (temp)
@@ -17459,9 +17457,9 @@ rs6000_output_function_epilogue (FILE *f
       rtx insn = get_last_insn ();
       /* If the last insn was a BARRIER, we don't have to write anything except
 	 the trace table.  */
-      if (GET_CODE (insn) == NOTE)
+      if (NOTE_P (insn))
 	insn = prev_nonnote_insn (insn);
-      if (insn == 0 ||  GET_CODE (insn) != BARRIER)
+      if (insn == 0 || !BARRIER_P (insn))
 	{
 	  /* This is slightly ugly, but at least we don't have two
 	     copies of the epilogue-emitting code.  */
@@ -17636,7 +17634,7 @@ rs6000_output_function_epilogue (FILE *f
 	      rtx parameter = DECL_INCOMING_RTL (decl);
 	      enum machine_mode mode = GET_MODE (parameter);
 
-	      if (GET_CODE (parameter) == REG)
+	      if (REG_P (parameter))
 		{
 		  if (SCALAR_FLOAT_MODE_P (mode))
 		    {
@@ -18231,7 +18229,7 @@ output_toc (FILE *file, rtx x, int label
 	}
     }
   else if (GET_MODE (x) == VOIDmode
-	   && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
+	   && (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE))
     {
       unsigned HOST_WIDE_INT low;
       HOST_WIDE_INT high;
@@ -18739,8 +18737,8 @@ rs6000_adjust_cost (rtx insn, rtx link, 
         if (rs6000_sched_groups
             && GET_CODE (PATTERN (insn)) == SET
             && GET_CODE (PATTERN (dep_insn)) == SET
-            && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
-            && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
+            && MEM_P (XEXP (PATTERN (insn), 1))
+            && MEM_P (XEXP (PATTERN (dep_insn), 0))
             && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
                 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
           return cost + 14;
@@ -19117,12 +19115,12 @@ adjacent_mem_locations (rtx insn1, rtx i
   rtx a = get_store_dest (PATTERN (insn1));
   rtx b = get_store_dest (PATTERN (insn2));
 
-  if ((GET_CODE (XEXP (a, 0)) == REG
+  if ((REG_P (XEXP (a, 0))
        || (GET_CODE (XEXP (a, 0)) == PLUS
-	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
-      && (GET_CODE (XEXP (b, 0)) == REG
+	   && CONST_INT_P (XEXP (XEXP (a, 0), 1))))
+      && (REG_P (XEXP (b, 0))
 	  || (GET_CODE (XEXP (b, 0)) == PLUS
-	      && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
+	      && CONST_INT_P (XEXP (XEXP (b, 0), 1)))))
     {
       HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
       rtx reg0, reg1;
@@ -19340,7 +19338,7 @@ is_mem_ref (rtx pat)
       && XINT (pat, 1) == UNSPEC_TIE)
     return false;
 
-  if (GET_CODE (pat) == MEM)
+  if (MEM_P (pat))
     return true;
 
   /* Recursively process the pattern.  */
@@ -19389,7 +19387,7 @@ is_load_insn (rtx insn)
   if (!insn || !INSN_P (insn))
     return false;
 
-  if (GET_CODE (insn) == CALL_INSN)
+  if (CALL_P (insn))
     return false;
 
   return is_load_insn1 (PATTERN (insn));
@@ -19808,7 +19806,7 @@ insn_must_be_first_in_group (rtx insn)
 
   if (!insn
       || insn == NULL_RTX
-      || GET_CODE (insn) == NOTE
+      || NOTE_P (insn)
       || GET_CODE (PATTERN (insn)) == USE
       || GET_CODE (PATTERN (insn)) == CLOBBER)
     return false;
@@ -19904,7 +19902,7 @@ insn_must_be_last_in_group (rtx insn)
 
   if (!insn
       || insn == NULL_RTX
-      || GET_CODE (insn) == NOTE
+      || NOTE_P (insn)
       || GET_CODE (PATTERN (insn)) == USE
       || GET_CODE (PATTERN (insn)) == CLOBBER)
     return false;
@@ -20898,10 +20896,10 @@ find_addr_reg (rtx addr)
 {
   while (GET_CODE (addr) == PLUS)
     {
-      if (GET_CODE (XEXP (addr, 0)) == REG
+      if (REG_P (XEXP (addr, 0))
 	  && REGNO (XEXP (addr, 0)) != 0)
 	addr = XEXP (addr, 0);
-      else if (GET_CODE (XEXP (addr, 1)) == REG
+      else if (REG_P (XEXP (addr, 1))
 	       && REGNO (XEXP (addr, 1)) != 0)
 	addr = XEXP (addr, 1);
       else if (CONSTANT_P (XEXP (addr, 0)))
@@ -20911,7 +20909,7 @@ find_addr_reg (rtx addr)
       else
 	gcc_unreachable ();
     }
-  gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
+  gcc_assert (REG_P (addr) && REGNO (addr) != 0);
   return addr;
 }
 
@@ -21207,7 +21205,7 @@ rs6000_machopic_legitimize_pic_address (
 	rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
 						Pmode, reg);
 
-      if (GET_CODE (offset) == CONST_INT)
+      if (CONST_INT_P (offset))
 	{
 	  if (SMALL_INT (offset))
 	    return plus_constant (base, INTVAL (offset));
@@ -21859,7 +21857,7 @@ rs6000_rtx_costs (rtx x, int code, int o
       return false;
 
     case MULT:
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (x, 1))
 	  && satisfies_constraint_I (XEXP (x, 1)))
 	{
 	  if (INTVAL (XEXP (x, 1)) >= -256
@@ -21894,7 +21892,7 @@ rs6000_rtx_costs (rtx x, int code, int o
 
     case UDIV:
     case UMOD:
-      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+      if (CONST_INT_P (XEXP (x, 1))
 	  && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
 	{
 	  if (code == DIV || code == MOD)
@@ -21964,7 +21962,7 @@ rs6000_rtx_costs (rtx x, int code, int o
 
     case SIGN_EXTEND:
     case ZERO_EXTEND:
-      if (GET_CODE (XEXP (x, 0)) == MEM)
+      if (MEM_P (XEXP (x, 0)))
 	*total = 0;
       else
 	*total = COSTS_N_INSNS (1);
Index: config/rs6000/rs6000.md
===================================================================
--- config/rs6000/rs6000.md	(revision 148116)
+++ config/rs6000/rs6000.md	(working copy)
@@ -1452,7 +1452,7 @@ (define_expand "strlensi"
   rtx addr, scratch_string, word1, word2, scratch_dlmzb;
   rtx loop_label, end_label, mem, cr0, cond;
   if (search_char != const0_rtx
-      || GET_CODE (align) != CONST_INT
+      || !CONST_INT_P (align)
       || INTVAL (align) < 8)
         FAIL;
   word1 = gen_reg_rtx (SImode);
@@ -1517,7 +1517,7 @@ (define_expand "add<mode>3"
       if (non_short_cint_operand (operands[2], DImode))
 	FAIL;
     }
-  else if (GET_CODE (operands[2]) == CONST_INT
+  else if (CONST_INT_P (operands[2])
 	   && ! add_operand (operands[2], <MODE>mode))
     {
       rtx tmp = ((!can_create_pseudo_p ()
@@ -1823,7 +1823,7 @@ (define_expand "sub<mode>3"
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT)
+  if (CONST_INT_P (operands[2]))
     {
       emit_insn (gen_add<mode>3 (operands[0], operands[1],
 				 negate_rtx (<MODE>mode, operands[2])));
@@ -2517,7 +2517,7 @@ (define_expand "div<mode>3"
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) > 0
       && exact_log2 (INTVAL (operands[2])) >= 0)
     ;
@@ -2573,7 +2573,7 @@ (define_expand "mod<mode>3"
   rtx temp1;
   rtx temp2;
 
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) <= 0
       || (i = exact_log2 (INTVAL (operands[2]))) < 0)
     FAIL;
@@ -2739,7 +2739,7 @@ (define_expand "udivmodsi4"
         FAIL;
     }
 
-  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
+  if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) < 0)
     {
       operands[2] = force_reg (SImode, operands[2]);
       label = gen_label_rtx ();
@@ -3068,7 +3068,7 @@ (define_expand "iorsi3"
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && ! logical_operand (operands[2], SImode))
     {
       HOST_WIDE_INT value = INTVAL (operands[2]);
@@ -3090,7 +3090,7 @@ (define_expand "xorsi3"
   ""
   "
 {
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && ! logical_operand (operands[2], SImode))
     {
       HOST_WIDE_INT value = INTVAL (operands[2]);
@@ -6304,11 +6304,11 @@ (define_insn "*adddi3_noppc64"
   "*
 {
   if (WORDS_BIG_ENDIAN)
-    return (GET_CODE (operands[2])) != CONST_INT
+    return (!CONST_INT_P (operands[2]))
 	    ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
 	    : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
   else
-    return (GET_CODE (operands[2])) != CONST_INT
+    return (!CONST_INT_P (operands[2]))
 	    ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
 	    : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
 }"
@@ -6323,11 +6323,11 @@ (define_insn "*subdi3_noppc64"
   "*
 {
   if (WORDS_BIG_ENDIAN)
-    return (GET_CODE (operands[1]) != CONST_INT)
+    return (!CONST_INT_P (operands[1]))
 	    ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
 	    : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
   else
-    return (GET_CODE (operands[1]) != CONST_INT)
+    return (!CONST_INT_P (operands[1]))
 	    ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
 	    : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
 }"
@@ -7502,12 +7502,12 @@ (define_expand "ashrdi3"
 {
   if (TARGET_POWERPC64)
     ;
-  else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
+  else if (TARGET_POWER && CONST_INT_P (operands[2]))
     {
       emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
       DONE;
     }
-  else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
+  else if (TARGET_32BIT && CONST_INT_P (operands[2])
 	   && WORDS_BIG_ENDIAN)
     {
       emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
@@ -7782,7 +7782,7 @@ (define_expand "iordi3"
 		  || rtx_equal_p (operands[0], operands[1]))
 		 ? operands[0] : gen_reg_rtx (DImode));
 
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
         {
           value = INTVAL (operands[2]);
 	  emit_insn (gen_iordi3 (tmp, operands[1],
@@ -7816,7 +7816,7 @@ (define_expand "xordi3"
 		  || rtx_equal_p (operands[0], operands[1]))
 		 ? operands[0] : gen_reg_rtx (DImode));
 
-      if (GET_CODE (operands[2]) == CONST_INT)
+      if (CONST_INT_P (operands[2]))
         {
           value = INTVAL (operands[2]);
 	  emit_insn (gen_xordi3 (tmp, operands[1],
@@ -8335,9 +8335,9 @@ (define_split
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(match_operand:SF 1 "const_double_operand" ""))]
   "reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
   "
@@ -8411,9 +8411,9 @@ (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(match_operand:DF 1 "const_int_operand" ""))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 1))]
@@ -8436,9 +8436,9 @@ (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(match_operand:DF 1 "const_double_operand" ""))]
   "! TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
@@ -8461,9 +8461,9 @@ (define_split
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(match_operand:DF 1 "const_double_operand" ""))]
   "TARGET_POWERPC64 && reload_completed
-   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
+   && ((REG_P (operands[0]) && REGNO (operands[0]) <= 31)
        || (GET_CODE (operands[0]) == SUBREG
-	   && GET_CODE (SUBREG_REG (operands[0])) == REG
+	   && REG_P (SUBREG_REG (operands[0]))
 	   && REGNO (SUBREG_REG (operands[0])) <= 31))"
   [(set (match_dup 2) (match_dup 3))]
   "
@@ -8518,7 +8518,7 @@ (define_insn "*movdf_hardfloat32"
 	return \"mr %0,%1\;mr %L0,%L1\";
     case 1:
       if (rs6000_offsettable_memref_p (operands[1])
-	  || (GET_CODE (operands[1]) == MEM
+	  || (MEM_P (operands[1])
 	      && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
 		  || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
 		  || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
@@ -8559,7 +8559,7 @@ (define_insn "*movdf_hardfloat32"
 	}
     case 2:
       if (rs6000_offsettable_memref_p (operands[0])
-	  || (GET_CODE (operands[0]) == MEM
+	  || (MEM_P (operands[0])
 	      && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
 		  || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
 		  || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
@@ -9283,7 +9283,7 @@ (define_split
       operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
       operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
     }
-  else if (GET_CODE (operands[1]) == CONST_INT)
+  else if (CONST_INT_P (operands[1]))
     {
       operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
       operands[5] = operands[1];
@@ -9315,11 +9315,11 @@ (define_expand "load_multiple"
   /* Support only loading a constant number of fixed-point registers from
      memory and only bother with this if more than two; the machine
      doesn't support more than eight.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) <= 2
       || INTVAL (operands[2]) > 8
-      || GET_CODE (operands[1]) != MEM
-      || GET_CODE (operands[0]) != REG
+      || !MEM_P (operands[1])
+      || !REG_P (operands[0])
       || REGNO (operands[0]) >= 32)
     FAIL;
 
@@ -9467,11 +9467,11 @@ (define_expand "store_multiple"
   /* Support only storing a constant number of fixed-point registers to
      memory and only bother with this if more than two; the machine
      doesn't support more than eight.  */
-  if (GET_CODE (operands[2]) != CONST_INT
+  if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) <= 2
       || INTVAL (operands[2]) > 8
-      || GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
+      || !MEM_P (operands[0])
+      || !REG_P (operands[1])
       || REGNO (operands[1]) >= 32)
     FAIL;
 
@@ -10692,7 +10692,7 @@ (define_expand "allocate_stack"
       emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
     }
 
-  if (GET_CODE (operands[1]) != CONST_INT
+  if (!CONST_INT_P (operands[1])
       || INTVAL (operands[1]) < -32767
       || INTVAL (operands[1]) > 32768)
     {
@@ -11044,8 +11044,8 @@ (define_expand "call"
     operands[0] = machopic_indirect_call_target (operands[0]);
 #endif
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
-  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
+  gcc_assert (MEM_P (operands[0]));
+  gcc_assert (CONST_INT_P (operands[1]));
 
   operands[0] = XEXP (operands[0], 0);
 
@@ -11095,8 +11095,8 @@ (define_expand "call_value"
     operands[1] = machopic_indirect_call_target (operands[1]);
 #endif
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (MEM_P (operands[1]));
+  gcc_assert (CONST_INT_P (operands[2]));
 
   operands[1] = XEXP (operands[1], 0);
 
@@ -11651,8 +11651,8 @@ (define_expand "sibcall"
     operands[0] = machopic_indirect_call_target (operands[0]);
 #endif
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
-  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
+  gcc_assert (MEM_P (operands[0]));
+  gcc_assert (CONST_INT_P (operands[1]));
 
   operands[0] = XEXP (operands[0], 0);
 }")
@@ -11841,8 +11841,8 @@ (define_expand "sibcall_value"
     operands[1] = machopic_indirect_call_target (operands[1]);
 #endif
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
-  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+  gcc_assert (MEM_P (operands[1]));
+  gcc_assert (CONST_INT_P (operands[2]));
 
   operands[1] = XEXP (operands[1], 0);
 }")
@@ -11909,7 +11909,7 @@ (define_expand "cbranch<mode>4"
 {
   /* Take care of the possibility that operands[2] might be negative but
      this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[2]) == CONST_INT
+  if (CONST_INT_P (operands[2])
       && INTVAL (operands[2]) < 0)
     {
       operands[2] = force_reg (<MODE>mode, operands[2]);
@@ -11944,7 +11944,7 @@ (define_expand "cstore<mode>4"
 {
   /* Take care of the possibility that operands[3] might be negative but
      this might be a logical operation.  That insn doesn't exist.  */
-  if (GET_CODE (operands[3]) == CONST_INT
+  if (CONST_INT_P (operands[3])
       && INTVAL (operands[3]) < 0)
     {
       operands[3] = force_reg (<MODE>mode, operands[3]);
@@ -12491,7 +12491,7 @@ (define_insn_and_split "*eq<mode>"
    (set (match_dup 0)
 	(lshiftrt:GPR (match_dup 0) (match_dup 4)))]
   {
-    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
+    if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 0)
       {
 	/* Use output operand as intermediate.  */
 	operands[3] = operands[0];
@@ -12531,7 +12531,7 @@ (define_insn_and_split "*eq<mode>_compar
 	      (set (match_dup 0)
 		   (lshiftrt:P (match_dup 0) (match_dup 5)))])]
   {
-    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
+    if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 0)
       {
 	/* Use output operand as intermediate.  */
 	operands[4] = operands[0];
@@ -12701,7 +12701,7 @@ (define_insn_and_split "*neg_eq<mode>"
   ""
   [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
   {
-    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
+    if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 0)
       {
 	/* Use output operand as intermediate.  */
 	operands[3] = operands[0];
@@ -14748,9 +14748,9 @@ (define_insn "*mtcrfsi"
         (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
 		    (match_operand 2 "immediate_operand" "n")]
 		   UNSPEC_MOVESI_TO_CR))]
-  "GET_CODE (operands[0]) == REG
+  "REG_P (operands[0])
    && CR_REGNO_P (REGNO (operands[0]))
-   && GET_CODE (operands[2]) == CONST_INT
+   && CONST_INT_P (operands[2])
    && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
   "mtcrf %R0,%1"
   [(set_attr "type" "mtcr")])
@@ -14855,7 +14855,7 @@ (define_insn "prefetch"
   "TARGET_POWERPC"
   "*
 {
-  if (GET_CODE (operands[0]) == REG)
+  if (REG_P (operands[0]))
     return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
   return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
 }"
Index: config/rs6000/sysv4.h
===================================================================
--- config/rs6000/sysv4.h	(revision 148116)
+++ config/rs6000/sysv4.h	(working copy)
@@ -400,7 +400,7 @@ do {									\
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
 	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X) 					\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
        || (!TARGET_NO_FP_IN_TOC						\
 	   && !TARGET_RELOCATABLE					\
Index: config/rs6000/xcoff.h
===================================================================
--- config/rs6000/xcoff.h	(revision 148116)
+++ config/rs6000/xcoff.h	(working copy)
@@ -80,7 +80,7 @@
        || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS	\
 	   && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF)		\
        || GET_CODE (X) == LABEL_REF					\
-       || (GET_CODE (X) == CONST_INT 					\
+       || (CONST_INT_P (X) 					\
 	   && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode))	\
        || (GET_CODE (X) == CONST_DOUBLE					\
 	   && (TARGET_MINIMAL_TOC					\

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