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Re: PATCH: Update classification of aggregates with __m256 ([AVX]: Update x86-64 psABI for aggregates with __m256)
On Wed, Feb 11, 2009 at 12:07:29PM -0800, H.J. Lu wrote:
> On Wed, Feb 11, 2009 at 10:16 AM, Harsha Jagasia <harsha.jagasia@amd.com> wrote:
> >> -------------
> >> @@ -5331,14 +5352,22 @@ construct_container (enum machine_mode m
> >> break;
> >> case X86_64_SSE_CLASS:
> >> if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
> >> - tmpmode = TImode;
> >> + {
> >> + if (regclass[i + 2] == X86_64_SSEUP_CLASS
> >> + || regclass[i + 3] == X86_64_SSEUP_CLASS)
> >> + tmpmode = OImode;
> >> + else
> >> + tmpmode = TImode;
> >> + }
> >>
> >
> >
> > I would think a check for n is needed here. If n is 2, regclass[i + 2] and regclass[i + 3] would not be valid, right?
> >
>
> This patch rewrites processing BLKmode with X86_64_SSE_CLASS.
> OK for trunk if there is no regression on Linux/x86-64?
>
No regression on Linux/x86-64. I am checking it in to fix my previous
change.
Thanks.
H.J.