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Re: [PATCH][MIPS][Loongson][SIMD] fix reduc_uplus_v8qi (biadd)
2009/2/4 Ruan Beihong <ruanbeihong@gmail.com>:
> The standard name 'reduc_uplus_m' require the same mode of input and output.
> When compiling some file in Mplayer, following error occurred:
>
> libfaad2/sbr_hfgen.c: In function 'hf_generation':
> libfaad2/sbr_hfgen.c:184: error: unrecognizable insn:
> (insn 562 561 563 69 libfaad2/sbr_hfgen.c:98 (set (reg:V8QI 618)
> (unspec:V4HI [
> (reg:V8QI 403 [ vect_var_.214 ])
> ] 515)) -1 (nil))
> libfaad2/sbr_hfgen.c:184: internal compiler error: in extract_insn, at
> recog.c:2027
>
> This patch fix the problem.
>
> The patch attached below:
> Index: gcc/config/mips/loongson.md
> ===================================================================
> --- gcc/config/mips/loongson.md (revision 143919)
> +++ gcc/config/mips/loongson.md (working copy)
> @@ -358,10 +358,13 @@
> [(set_attr "type" "fadd")])
>
> ;; Sum of unsigned byte integers.
> +;; NOTE: reduce_uplus_m need the same mode of input and output,
> +;; while biadd here actually return a V4HI with the lowerest field
> +;; set to the sum of 8 byte.
> (define_insn "reduc_uplus_<mode>"
> - [(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
> - (unspec:<V_stretch_half> [(match_operand:VB 1 "register_operand" "f")]
> - UNSPEC_LOONGSON_BIADD))]
> + [(set (match_operand:VB 0 "register_operand" "=f")
> + (unspec:VB [(match_operand:VB 1 "register_operand" "f")]
> + UNSPEC_LOONGSON_BIADD))]
> "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
> "biadd\t%0,%1"
> [(set_attr "type" "fabs")])
>
> --
> James Ruan
>
Ok. Here is the finished patch:
Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md (revision 143947)
+++ config/mips/loongson.md (working copy)
@@ -358,7 +358,19 @@
[(set_attr "type" "fadd")])
;; Sum of unsigned byte integers.
-(define_insn "reduc_uplus_<mode>"
+;; NOTE: reduce_uplus_m need the same mode of input and output,
+;; while biadd here actually return a V4HI with the lowerest field
+;; set to the sum of 8 byte.
+(define_insn "reduc_uplus_v8qi"
+ [(set (match_operand:VB 0 "register_operand" "=f")
+ (unspec:VB [(match_operand:VB 1 "register_operand" "f")]
+ UNSPEC_LOONGSON_BIADD))]
+ "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+ "biadd\t%0,%1"
+ [(set_attr "type" "fabs")])
+
+;; This is the actual biadd which can be used through builtin function call.
+(define_insn "loongson_biadd"
[(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
(unspec:<V_stretch_half> [(match_operand:VB 1 "register_operand" "f")]
UNSPEC_LOONGSON_BIADD))]
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c (revision 143947)
+++ config/mips/mips.c (working copy)
@@ -11253,7 +11253,6 @@
#define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
#define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
#define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
-#define CODE_FOR_loongson_biadd CODE_FOR_reduc_uplus_v8qi
#define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
#define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
#define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
--
James Ruan
Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md (revision 143947)
+++ config/mips/loongson.md (working copy)
@@ -358,7 +358,19 @@
[(set_attr "type" "fadd")])
;; Sum of unsigned byte integers.
-(define_insn "reduc_uplus_<mode>"
+;; NOTE: reduce_uplus_m need the same mode of input and output,
+;; while biadd here actually return a V4HI with the lowerest field
+;; set to the sum of 8 byte.
+(define_insn "reduc_uplus_v8qi"
+ [(set (match_operand:VB 0 "register_operand" "=f")
+ (unspec:VB [(match_operand:VB 1 "register_operand" "f")]
+ UNSPEC_LOONGSON_BIADD))]
+ "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+ "biadd\t%0,%1"
+ [(set_attr "type" "fabs")])
+
+;; This is the actual biadd which can be used through builtin function call.
+(define_insn "loongson_biadd"
[(set (match_operand:<V_stretch_half> 0 "register_operand" "=f")
(unspec:<V_stretch_half> [(match_operand:VB 1 "register_operand" "f")]
UNSPEC_LOONGSON_BIADD))]
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c (revision 143947)
+++ config/mips/mips.c (working copy)
@@ -11253,7 +11253,6 @@
#define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
#define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
#define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
-#define CODE_FOR_loongson_biadd CODE_FOR_reduc_uplus_v8qi
#define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
#define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
#define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3