This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Use FP reg for SI value -- powerpc-xilinx-eabi
- From: Michael Eager <eager at eagercon dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 23 Jan 2009 11:21:53 -0800
- Subject: Use FP reg for SI value -- powerpc-xilinx-eabi
The attached patch fixes a bug which showed up after
the previous patches were applied to a powerpc-xilinx-eabi
build, with single-precision FP registers.
In a PowerPC processor with double-precision FP registers,
the *movdi_internal1 template would allow storing DI values
in a double-precision FP register. The attached patch modifies
the *movsi_internal1 template to allow storing SI values in
single-precision FP registers. This pattern is never generated
in a configuration with double-precision FP registers.
Also fix function return register (probably should have been
in the previous patch) and fix the sense of the test for
single-precision FPU in *movdf_softfloat32.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
2009-01-23 Michael Eager <eager@eagercon.com>
* config/rs6000/rs6000.c: rs6000_function_value: set function return
reg for single-precision FPU
* config/rs6000/rs6000.md: *movsi_internal1: add pattern to move SI
values to/from single-precision FP regs.
*movdf_softfloat32: Correct test for single-precision FPU
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/rs6000.c gcc/gcc/config/rs6000/rs6000.c
--- gcc-orig/gcc/config/rs6000/rs6000.c 2009-01-21 13:26:21.000000000 -0800
+++ gcc/gcc/config/rs6000/rs6000.c 2009-01-21 13:27:48.000000000 -0800
@@ -22576,7 +22576,8 @@ rs6000_function_value (const_tree valtyp
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
- else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
+ && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
regno = FP_ARG_RETURN;
else if (TREE_CODE (valtype) == COMPLEX_TYPE
&& targetm.calls.split_complex_arg)
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/rs6000.md gcc/gcc/config/rs6000/rs6000.md
--- gcc-orig/gcc/config/rs6000/rs6000.md 2009-01-21 13:26:21.000000000 -0800
+++ gcc/gcc/config/rs6000/rs6000.md 2009-01-21 13:27:48.000000000 -0800
@@ -8179,8 +8179,8 @@
(set_attr "length" "4")])
(define_insn "*movsi_internal1"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
+ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,*f,m"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
@@ -8196,9 +8196,11 @@
mt%0 %1
mt%0 %1
mt%0 %1
- {cror 0,0,0|nop}"
- [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
+ {cror 0,0,0|nop}
+ stfs%U0%X0 %1, %0
+ lfs%U1%X1 %0, %1"
+ [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
;; sequence.
@@ -8609,7 +8611,7 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
"! TARGET_POWERPC64
- && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
+ && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"