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[PATCH, i386]: Generate mfence for 64bit targets even with -mno-sse


Hello!

As pointed out by rth in a private mail, -mno-sse switch was introduced to generate code that doesn't clobber SSE registers. Since mfence doesn't use any, we can generate it even when -mno-sse is in effect.

2008-11-26 Uros Bizjak <ubizjak@gmail.com>

   * config/i386/sync.md (memory_barrier_nosse): Disable also for
   TARGET_64BIT.  Remove special asm template for TARGET_64BIT case.
   (memory_barrier): Do not generate memory_barrier_nosse instruction
   for TARGET_64BIT.
   * config/i386/sse.md (*sse2_mfence): Also enable for TARGET_64BIT.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}. Patch is committed to SVN.

Uros.
Index: sse.md
===================================================================
--- sse.md	(revision 142222)
+++ sse.md	(working copy)
@@ -7719,7 +7719,7 @@
 (define_insn "*sse2_mfence"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
-  "TARGET_SSE2"
+  "TARGET_64BIT || TARGET_SSE2"
   "mfence"
   [(set_attr "type" "sse")
    (set_attr "memory" "unknown")])
Index: sync.md
===================================================================
--- sync.md	(revision 142222)
+++ sync.md	(working copy)
@@ -39,7 +39,7 @@
   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
   MEM_VOLATILE_P (operands[0]) = 1;
 
-  if (!TARGET_SSE2)
+  if (!(TARGET_64BIT || TARGET_SSE2))
     {
       emit_insn (gen_memory_barrier_nosse (operands[0]));
       DONE;
@@ -50,14 +50,8 @@
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
    (clobber (reg:CC FLAGS_REG))]
-
-  "!TARGET_SSE2"
-{
-  if (TARGET_64BIT)
-    return "lock{%;| }or{q}\t{$0, (%%rsp)|QWORD PTR [rsp], 0}";
-  else
-    return "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}";
-}
+  "!(TARGET_64BIT || TARGET_SSE2)"
+  "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
   [(set_attr "memory" "unknown")])
 
 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode

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