This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PING] Move costs, allocno costs, and per-register costs


Richard Sandiford wrote:
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg00325.html
Fixes a problem with the costs of union classes.  Needed to fix
MIPS dspr2-MULT{,U}.c regressions.

Sorry, Richard. I missed that email. I had some problems with my email (an still messages for some time is lost).

You did a big job comparing so many targets. I know about the problem. Recently I tried to modify IRA (Chaitin-Briggs algorithm) to permit allocnos to be of union of cover classes. It could solve the problem you are trying to solve by using smaller cover classes. It also could solve one IRA drawback in comparison with the old RA. Memory-memory movements (like arr[i] = arr [j]) are implemented usually as two insns using a temporary register. The temporary register could be of two cover classes (e.g. general purpose or float regs). Unfortunately, I had no improvement for main stream architectures and sometime I had a degradation (e.g. when the temporary register can not be trivially colored as a general register, the float register was used on x86. But the temporary register can be still colored although it is not *trivially* colored. As the result IRA used slower insns of float register load and store and generated a slower code).

Anyway, I'd like to investigate your patch more and runs SPEC benchmarks for it. I think I'll give you a feedback on this week or at the beginning of the next week.

Thanks for approaching this problem.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]